Dependable Nano Computing

In the Dependable Nano Computing pillar, the following topics are researched:

  1. Computation Paradigms and Programmability: Currently, there is a wide gap between research on Nano-scale devices and research on their utilization in computer technology. Essentially these new Nano-devices appear to exhibit behaviours that are substantially different than that of the well-established MOS devices. In our opinion this calls for novel computation paradigms and design methodologies. We strongly believe that the tomorrow's replacement of the MOS transistor will not just be a MOS-alike device build with a different technology. We are aware of the tremendous implications of such a major paradigm change but if we are to fully utilize the potential of these emerging devices we should adapt the paradigms to their specifics. We do not suggest that traditional CMOS based electrical and computer engineering will cease to exist in the near future and we will continue working in Nano-CMOS specific computation platform but we think that one has to keep pace with the new emerging technologies as eventually they will become dominant.

  2. Design and Test Methodologies: Unpredictability, variability and reliability are example of inherent acute Nano-scale device specific problems that are certainly changing the way we design and test computer systems. Device parameter variations together with some other sources of variance, e.g., temperature and power supply variations are causing significant fluctuations in the time required by a part of a circuit to perform its computational task. Delay variations have been mainly dealt with by using over-design, i.e., sufficient large margins are used to ensure that each part of the chip has enough time to finish its work. As the impact of delay variations increases with downscaling, for near future technologies this will lead to excessive margins, resulting in large performance losses (a generation of fabrication technology improvement can be lost). The low reliability and large Nano device specific fault density make most of the well-known fault tolerant technique less effective. The previously mentioned aspect calls for an integrated approach where variability and reliability issues are dealt with at all levels starting form technology and device up to the system. In view those we consider research related to introspective generic architectures and associated design methodologies that enable circuit and system designers to seamlessly incorporate design for variability, design for reliability, and life time diagnosis support in their designs of premium importance for deep sub-micron CMOS fabrication technologies as well as for other alternative Nano-technologies.

  3. Another important aspect, also boosted by nanotechnology, which may change the way computation will be done in the near future, is the possibility to construct highly parallel and programmable (reconfigurable) structures, which may or may not follow "traditional" organizations. Many problems have still to be solved in this domain and we expect that major changes have to be operated in the way one programmes and maps applications on such Nano-computation platforms. To deal with the increased complexity of the modern applications, with the tight energy constraints, and to be able to effectively exploit the huge amount of available resources, while keeping the pace with a very dynamic market, one needs the appropriate tools and also a change in perception and mentality. Composability, predictability, scalability, and programmability are some of the "-ities" that lay at the foundation of successful complexity management.

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