The Computer Engineering laboratory (CE lab) has a long-standing tradition in performing fundamental research as well bridging research and practice to serve the industry and society needs. The conducted research covers a broad range of topics ranging from computer architecture, computer arithmetic, electronic design and test to compiler construction, while focusing both on embedded systems as well as high performance computing without losing sight of future and emerging technologies.

In this tradition, the CE researchers in the CE lab are driven by their scientific curiosity to investigate industrially and societally relevant issues and providing solutions with a large industrial impact; national and international industrial collaboration is an integral part of our research activities. It is therefore no surprise that many directions identified in our research themes perfectly fit with international roadmaps such as the International Technology Roadmap for Semiconductors (ITRS) of the semi-conductor industry and the HiPeac European Network of Excellence that try to sketch the challenges of our field for the next coming years. There are three major challenges driving the research choices at the CE Laboratory:

  1. Technology scaling: Technology scaling is posing new architectural, design, and computing challenges. E.g., variability of the manufacturing process will lead to decreased reliability at the transistor level; this necessitates investigating radically new ways of design and computing that are no longer necessary deterministic in nature.

  2. More Moore and more than Moore: Due to the transistor density (more Moore) and the ever-increasing demand for improved functionality (more than Moore), systems become increasingly complex. In order to address bottlenecks such as memory, power, and frequency, multi-core architectures have been introduced. Scalability of such architectures adopting the Von-Neumann paradigm is limited, so other computing paradigms need to be explored [1]. One way to utilize the abundance of transistors is to build reconfigurable fabrics on a chip in order to add (hardware) flexibility and improve performance through parallel processing.

  3. Complexity of future systems: Due to the above-mentioned increased System-on-Chip (SoC) complexity where adaptivity, reconfigurability and composability are viewed as key system features, there is a rising need for improved support of the design process that goes beyond, e.g., mere RTL design. HW/SW co-design, partitioning, and mapping on multiprocessor System-on-Chips (MPSoCs) as well as Application Specific Instruction Set Processor (ASIP) design are new design approaches and technologies that allow system developers to explore in a time and cost efficient way what the impact is of certain architectural choices.

The above identified challenges and the curiosity driven research have led to the definition of three research pillars that organize the research activities in the CE lab. They  consist of: 

  1. Dependable Nano Computing
  2. Big Data Architectures
  3. Liquid Architectures
  4. In-Memory Computing
  5. Quantum Computing





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