Nader Khammassi

Researcher at the Quantum and Computer Engineering Lab of the Faculty of Engineering, Mathematics and Computer Science (EEMCS/EWI), Delft University of Technology.


Dr. Nader Khammassi joined the Quantum Computing Lab at the Delft University of Technology in the Netherlands in 2016. He is working at QuTech in collaboration with Intel to design a scalable quantum computer architecture based on superconducting qubit and spin qubit technologies.


The initial topic of his research was focusing on high performance simulation of quantum computers. He developed a universal quantum computer simulator named QX, and started creating tools around QX to investigate the different layers of the quantum computer architecture being developed at QuTech. In 2016, the focus of his research was extended to the compilation of quantum algorithms through designing a new quantum programming framework called OpenQL. He contributed to the demonstration of the full architecture stack of a quantum computer from Software down to both the Hardware on both Superconducting qubits and Si-Spin qubit. Currently, his work is focusing on the design of a scalable micro-architecture and in extending its support to the Si-spin Qubits.

Publications Nader Khammassi

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  1. N. Khammassi, G. G. Guerreschi, I. Ashraf, J. W. Hogaboam, C.G. Almudever, K.L.M. Bertels, cQASM v1.0: Towards a Common Quantum Assembly Language1706_cqasm_v10_towards_a_common_quantum_assembly_language.pdf (to appear: May 2018), Quantum Science and Technology (QST) [Journal Paper]
  2. X. Fu, M. A. Rol, C.C. Bultink, J. van Someren, N. Khammassi, I. Ashraf, R.F.L. Vermeulen, J. C. de Sterke, W.J. Vlothuizen, R. N. Schouten, C.G. Almudever, L. DiCarlo, K.L.M. Bertels, A Microarchitecture for a Superconducting Quantum Processor1695_a_microarchitecture_for_a_superconducting_quantum_processor.pdf (May 2018), IEEE Micro, volume 38, issue 3, Top Picks from the 2017 Computer Architecture Conferences [Journal Paper]
  3. L. Lao, B. van Wee, I. Ashraf, J. van Someren, N. Khammassi, K.L.M. Bertels, C.G. Almudever, Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures1707_mapping_of_lattice_surgerybased_quantum_circuits_on_surfac.pdf (May 2018), arXiv:1805.11127 [Technical Report]
  4. 2017

  5. I. Ashraf, N. Khammassi, M. Taouil, K.L.M. Bertels, Memory and Communication Profiling for Accelerator-based Platforms1681_memory_and_communication_profiling_for_acceleratorbased_pl.pdf (December 2017), IEEE Transactions on Computers (TC) , volume PP, issue 29, Pre-print [Journal Paper]
  6. X. Fu, M. A. Rol, C.C. Bultink, J. van Someren, N. Khammassi, I. Ashraf, R.F.L. Vermeulen, J. C. de Sterke, W.J. Vlothuizen, R.N. Schouten, C.G. Almudever, L. DiCarlo, K.L.M. Bertels, An Experimental Microarchitecture for a Superconducting Quantum Processor1693_an_experimental_microarchitecture_for_a_superconducting_qua.pdf (October 2017), 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2017), 14-18 October 2017, Boston, USA, Best Paper Award [Conference Proceedings]
  7. C.G. Almudever, L. Lao, X. Fu, N. Khammassi, I. Ashraf, D. Iorga, S. Varsamopulos, C. Eichler, A. Wallraff, L. Geck, A. Kruth, J. Knoch, H. Bluhm, K.L.M. Bertels, The Engineering Challenges in Quantum Computing (March 2017), Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland [Conference Proceedings]
  8. N. Khammassi, I. Ashraf, X. Fu, C.G. Almudever, K.L.M. Bertels, QX: A High-Performance Quantum Computer Simulation Platform (March 2017), Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland [Conference Proceedings]
  9. 2015

  10. I. Ashraf, K.L.M. Bertels, N. Khammassi, J.C. Le Lann, Communication-aware Parallelization Strategies for High Performance Applications1487_communicationaware_parallelization_strategies_for_high_per.pdf (July 2015), IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 08-10 July 2015, Montpellier, France [Conference Paper]
  11. 2014

  12. N. Khammassi, High-level Structured Programming Models for Explicit and Automatic Parallelization on Multicore Architectures (December 2014), [Phd Thesis]
  13. N. Khammassi, J.C. Le Lann, XPU: A C++ Metaprogramming Approach to Ease Parallelism Expression: Parallelization Methodology, Internal Design and Practical Application (November 2014), Chapter "Parallel Programming: Practical Aspects, Models and Current Limitations", Published by Nova Science Publishers, Inc., Hauppauge, NY, USA [Book Chapter]
  14. N. Khammassi, J.C. Le Lann, A High-Level Programming Model to Ease Pipeline Parallelism Expression On Shared Memory Multicore Architectures (April 2014), ACM High Performance Computing Symposium (HPC 2014), 13-16 April 2014, Tampa, USA, HPC '14 Proceedings of the High Performance Computing Symposium Article No. 9 [Conference Proceedings]
  15. N. Khammassi, J.C. Le Lann, Design and Implementation Of A Cache Hierarchy-Aware Task Scheduling For Parallel Loops On Multicore Architectures (February 2014), Third International conference on Parallel, Distributed Computing technologies and Applications (PDCTA 2014), 3-10 February 2014, Sydney, Australia [Conference Proceedings]
  16. N. Khammassi, J.C. Le Lann, Tackling Real-Time Signal Processing Applications on Shared Memory Multicore Architectures Using XPU (February 2014), Embedded Real Time Software and Systems (ERTS 2014), 5-7 Februari 2014, Toulouse, France [Conference Proceedings]
  17. 2012

  18. N. Khammassi, J.C. Le Lann, J.Ph. Diguet, A. Skrzyniarz, MHPM: Multi-Scale Hybrid Programming Model: A Flexible Parallelization Methodology (June 2012), IEEE International Conference on High Performance Computing (HPCC 2012), 25-27 June 2012, Liverpool, United Kindom, Liverpool, UK [Conference Proceedings]