Quantum Engineering Colloquium


1. Daniel Kraak,  TU Delft, The Netherlands -- 05-07-2017

2. Lingling Lao, TU Delft, The Netherlands -- 05-07-2017


 1. Mitigation of Sense Amplifier Degradation Using Input Switching

Designers typically add design margins to compensate for time-zero (due to process variation) and time-dependent (due to e.g., Bias Temperature Instability (BTI)) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory’s Sense Amplifier (SA). For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e., an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, workload).

2. Mapping  fault-tolerant  quantum  circuits  on  qubit  plane  architectures

When adopting the circuit model as a computational model, quantum algorithms can be represented by quantum circuits consists of qubits and gates. Such a circuit description assumes that any kind of interaction between qubits is possible and both qubits and gates are perfect. However, the quantum hardware is error prone and in real quantum experimental platforms the physical qubit layout limits qubit interactions. Therefore, compiler passes are required for making quantum circuits fault-tolerant (FT) and mapping them on a specific physical quantum architecture.  In this presentation, I will discuss how to efficiently map FT quantum circuits onto surface code architectures.





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