Opportunities and Challenges for the Nanometric Design of Post-CMOS Memories

Speaker

Prof. Lombardi from Northeastern University (Boston, USA)  -- 08-05-2014

Abstract

This talk will present new developments in the design of memories using post-CMOS technologies. The MOSFET as basic device for CMOS implementation is fast moving in the deep nanometric scales (well below 32 nm), and its limitations for memory circuit design are starting to become evident, as reflected by issues related to capacity, stability, power dissipation and volatility.  Moreover new memory paradigms are being sought and emerging in a variety of applications. Among them, multi-level storage and non-volatile operation are very compelling features. New materials and physical phenomena have been proposed and utilized for commercially meeting these challenges, thus affecting circuit design; this talk will outline some of these new technologies (such as based on resistive phenomena for phase change and filament growth); trends, obstacles and possible solutions for the design of these memories will be presented and discussed.

Bio

Dr Fabrizio Lombardi is the holder of the International Test Conference (ITC) Endowed Chair Professorship at Northeastern University, Boston. Dr.  Lombardi is a Fellow of the IEEE and served twice as Editor in Chief of the IEEE Transactions on Computers, the flagship peer reviewed publication of the IEEE Computer Society.  Currently, Dr. Lombardi is the Inagural Editor in Chief of the IEEE Transactions on Emerging Topics in Computing as well as an Associate Editor of the IEEE Transactions on Nanotechnology. He serves as an elected Member of the Board of Governors of the IEEE Computer Society as well as the Administrative/Executive Boards of the IEEE Nanotechnology Council and the Computing-in-the-Core non-partisan advocacy coalition for K-12 Computer Science education. His research interests are nano manufacturing/computing, advanced memory architectures, embedded VLSI design and defect analysis/modeling.

Slides

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