PostDocs and Students

  • PostDocs
    • Motta Taouil
    • Peyman Pouyan
  • PhD Students
    • Ongoing
      • Computation-in-Memory PhD Students
        • 1. Du Nguyen Anh, Memristor based Computation-in-Memory (CIM) architecture for Big-Data.
        • 2. Lei Xie, Memristor Based Logic Circuit Design .
        • 3. Adib Haron, Mapping Parallel Algorithms on Memristor-based Computation-in-Memory (CIM) architecture..
        • 4. Jintao Yu, Compiler and Simulation Plaform for Computation-in-Memory (CIM) Architecture
        • 5. Muath Abu Lebdeh, Computation-in-Memory Circuit and Low Level Architecture and Modeling  
      • Test and Relaibility PhD students
        • 6.. Innocent Agbo, Memory Reliability in Nano-Era: Modeling, Monitoring and Design.
        • 7.. Daniel Kraak, Robust Memory Desigin-- Mitigation for aging.
        • 8. Lizhou Wu, Fault Models, Test, DFT and BIST for STT-MRAMs.
        • 9. Guilherme Medeiros, Testing FinFET memories.
        • 10. Prashant D. Joshi, Dependable Network Topologies 
      • Hardware Security PhD Students 
        • 11. Haji Akhundov, Design for secure systems.
        • 12. Troya Cagil Koylu, Design for Security.
        • 13. Shayesteh Masoumian, Novel PUF Technology (in collaboration with Intrinsic ID)
      • Graduduated
        1. Mafalda Cortez, Reliability Assessment and Test Methods for Anti-counterfeiting Technology, November 2015.
        2. Motta Taouil, Yield and Cost Analysis for 3D Stacked ICs, Septmeber 2014. Graduated with Cum Laude. 
        3. Seyab Khan, Bias Temperature Instability Analysis, Monitoring and Mitigation for Nano-Scaled Circuits, September 2013. 
        4. Zaidi Haron, Testability and Fault Tolerance for Emerging Nanoelectronic Memories, May 2012.
  •  Master Students
    •   Ongoing
      1. Moritz Fieback, DRAM Reliability Analysis
      2. Michael Mainemer Lang,  Quality and Cost modeling for 3D Stacked ICs
      3. Abdullah Aljuffri, Using Deep learning for Hardware attacks.
    •   Graduated
      1. Haji Akhundov, Development and Design of Lightweight public-key crypto core, in collaboration with Intrinsic ID (the Netherlands), Jan 2017.  
      2. Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
      3. Anteneh Gebregiorgis, Aging Mitigation Schemes for Embedded Memories, In collaboration with Karlsruhe Institute of Technology (KIT, Germany). July 2014
      4. Gijs Roelofs 'Design for Testability for Secure ICs', Master Thesis, CE-MS-2012-10, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven, the Netherlands, October 2013.
      5. Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.
      6. Abiram Pattabiraman, Experimental Wind Flow Studies For Development and Calibration Of Thermal Models For Photovoltaic Cells, Delft University of Technology, in collaboration with IMEC (Belgium), July 2013.
      7. Christos Papameletis, 'Design-for-Testability Automation for 3D Stacked ICs', Master Thesis, CE-MS-2012-09, Delft University of Technology, in collaboration with IMEC (Belgium) and Cadence (USA), Augustus 2012.
      8. Subin Sivadas, 'Sensorless Algorithm development for Field Oriented Motor Control', Master Thesis, CE-MS-2011-04, Delft University of Technology, in collaboration with NXP Nijmegen (the Netherlands), November 2011.
      9. Vahid Roostaie, Design and analysts of a coherent memory subsystem for FPGA-based embeddedsystems, Master Thesis, CE-MS-2011-16, Delft University of Technology, in collaboration with Vec-torFabrics B.V. Eindhoven, The Netherlands, September 2011.
      10. Apurva Dargar, 'Modeling SRAM start-up characteristics for Physical Unclonable Functions', Maste Thesis, CE-MS-2011-11, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven,the Netherlands, July 2011. Graduated with Cum Laude.
      11. Venkataraman Krishnaswami, 'A New Test Paradigm for Semiconductor Memories in the Nano-Era', Master Thesis, CE-MS-2011-14, Delft University of Technology, July 2011.
      12. Vishwas Raj Jain, 'A Hierarchical Memory Diagnosis Approach: dealing with defects in all parts of the memory system', Master Thesis, CE-MS-2011-15, Delft University of Technology, July 2011. Graduated with Cum Laude.
      13. Nivesh Rai, 'Defect Oriented Testing for Analog/Mixed-Signal Devices', Master Thesis, CE-MS-2011-10, Delft University of Technology, in collaboration with NXP Semiconductors, Eindhoven, July 2011.
      14. Imran Achraf, 'MePoEfAr: Memory and Power Efficient Architecture for EmbeddedMicrocontrollers', Master Thesis, CE-MS-2011-17, Delft University of Technology, July 2011.
      15. Halil Kukner, 'Generic and Orthogonal March Element based Memory BIST Engine' Master Thesis, CE-MS-2010-25, Delft University of Technology, September 2010.
      16. Jouke Verbree, 'On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture', Master Thesis, CE-MS-2010-xx, Delft University of Technology, in collaboration with IMEC, Belgium, July 2010.
      17. Zaiyan Ahyadi, 'Experimental Analysis on ECC Schemes for Fault Tolerant Hybrid Memories', Master Thesis, CE-MS-2009-xx, Delft University of Technology, November 2009.
      18. Ghazaleh Nazarian, 'On-Line Testing for Routers in Networks on Chip', Master Thesis, CE-MS-2008-xx, Delft university of Technology, December 2008.
      19. Fomin Nkengafeh Anne, 'Experimental Analysis of Design-For-Testability Techniques in SRAMs', Master Thesis, CE-MS-2008-xx, Delft university of Technology, October 2008.
      20. Li Chuanyou, 'Testing Deep-submicron Embedded Memories in FPGAs', Master Thesis, CE-MS-2008-xx, Delft University of Technology in collaboration with Altera, San Jose, CA, USA, August 2008.
Said Hamdioui