Research

I have been working on two main research lines: Dependability and Emerging Computing paradigms based on emerging device technologies.

  • Dependability
    • I have been working on different aspects related to dependability while collaborating with many universities and companies.
    • Testability: This includes understanding the weaknesses of new technology nodes and integration, develop appropriate schemes that can enhance the outgoing product quality and reduce the cost. I have been strongly collaborating with companies such as NXP, IMEC, Qualcomm, Cadence, etc. as well as with universities such as Polito Di Torino.
    • Reliability: This includes the analysis of reliability failure mechanism on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc. I have established a structural collaboration with IMEC on this topic; IMEC is one of the leading companies in the world when it comes to analyzing reliability of cutting edge technologies. In addition, I have a bilateral project with ESA (European Space Agency) on this topic. Collaboration has also been taking place with NXP and Karlsruhe Institute of Technology in Germany.
    • Hardware Security: This includes Physical Unclonable Functions technology for strong security and authentication solutions, Development & design & of secure ICs, etc. I have been collaborating with Intrinsic ID (NL) on this topic as well as with LIRMM in France.
      • Emerging Computing paradigms
        • In addition to the above topics, I have started working on emerging computing paradigms using novel devices. In this context, I have developed a new architecture (CIM100X), based on Computation-In-Memory using memristor devices for data-intensive applications. All implementation aspects of such architecture are under investigation, including:
        • Circuit design: in which logic and arithmetic operations are developed and designed based on resistive devices and by integrating the function within the crossbar memory.
        • Architecture design: where different crossbar architectures are investigated while considering different metrics such as optimization of communication, power and control logic, as well as maximizing the parallelism and throughput.
        • Compiler Level: in which a programming interface and the mapping of the parallel algorithms on the crossbar architecture are under study.
        • Application level: in which applications and algorithms supporting massive parallelism are investigated in order to analyze their suitability for CIM100X architecture.
Said Hamdioui