[CE2012-2] ST-Ericsson (FR) - Adaptive Voltage Scaling and IC Production Testing

Many processor chips manufactured today apply voltage scaling to reduce power consumption and ensure reliable functionality under process variability. Traditional techniques to voltage scaling require running devices at worst-case voltage conditions, which leads to additional power consumption, and to increasing design margins. Adaptive voltage scaling technique makes it possible to use an optimal voltage setting per IC to compensate for process & temperature variations. The challenge is to be able to determine in an accurate manner the performance of the die at a specific voltage, and also to compensate for intra-die variations. Adaptive voltage scaling will also affect traditional IC production testing since design margins are minimized for each die in a real application, and hence leads to some adaptive testing by reducing test margins as well. Since manufacturing and application environments can be different, test margins must be carefully analyzed to avoid potential yield overkill.

Problem statement:
The first issue is to generate an equation to accurately predict the minimum estimated transistor voltage per IC, relying on a variety of ring oscillators with different properties (transistors, RC), and on structural testing (ATPG, MBIST). The second issue is to define specific design rules (ring oscillator layout placements, properties, design rules) to improve equation accuracy.

Expected effort:
A good working knowledge of statistics and regression will be appreciated. The candidate should be able to understand digital CAD flow from RTL to GDS. The following tasks need to be carried out.

Task 1: 28n-32n SoC test data analysis to check for best predictors
Task 2: Equation generation and yield estimation modeling
Task 3: AVS test flow requirements
Task 4: IC design variability analysis

Company Name: ST-Ericsson
Location: Grenoble, France
Start date: April 1, 2012
Duration: 9 months
Number of positions: 1 MSc

CE Tweets