MSc Internships

Admission procedure for industrial projects.

If you are a MSc student in Computer Engineering (CE) interested in working in a project in the industry, please follow the procedure described below:

  1. Prepare a curriculum vitae (CV) and a course list with all grades (your GPA should be above 7).
  2. Send both CV and course/grade list to Zaid Al-Ars (Z.Al-Ars_AT_tudelft.nl).
  3. Indicate the project(s) of your interest (see below). In case you find none, please contact Zaid Al-Ars for the most recent openings.

Your application will be forwarded to the company contacts and you will be notified if if your application has been accepted. An invitation for an interview can be part of the application procedure.

If you are accepted by the company:

  • Write a one page description of your specific project topic.
  • A CE supervisor will be assigned to guide you from the university side based on your topic.

It is strongly advised that the student has finished most course work before applying for an MSc project in the industry. Furthermore, international MSc students may require a 'work permit' before they can start their work. Obtaining such a permit may take approximately 2 months, so it is advisable to start looking early for an open position and to start your preparatory work while waiting for the permit to be issued. More information can be found on this page.

If you're interested in performing an internship in the industry and would like to get credit points based on your work, please follow the procedure as outlined on this page. It is also possible for students to find industrial MSc projects by themselves. In this case, the project must be approved first. You should contact Zaid Al-Ars for more details on how to obtain approval.

MSc Internship Projects

[CE2017-2] Xilinx Research (IE) - High-Level Programmability of Heterogeneous Multicore ARM-FPGA System

Xilinx is a world leading maker of FPGA devices. The internship will take place in Xilinx Research Labs Ireland in the Dublin site. The team's focus within the Research Labs in Dublin is to investigate the high-level programmability of signal processing algorithms and conduct experiments with new programming paradigms for Xilinx FPGAs, SoCs. In particular, current generation Xilinx Zynq devices with two ARM cores and programmable FPGA logic side by side are an interesting field of investigation.

The intern will be responsible for optimizing and verifying the implementation of the specified applications on these compute platforms. Additionally, he/she will gain valuable insights into the development process in an industrial research lab. The ideal candidate will be a student working toward a bachelor's or master's degree from an accredited academic institute, with a strong background in software programming. No detailed RTL/FPGA experience is required.

Company Name: Xilinx
Location: Dublin, IE
Start date: Begining 2017
Duration: 3-9 months
Position: Internship or MSc thesis student

 

[CE2017-1] Ximedes Software (NL) - Implementing Blockchain Solution for Secure Payment Transactions

Ximedes is a FinTech company, based in Haarlem, that offers software development services and transaction based solutions. As part of their effort to integrate new developments in payment transaction, they are interested in Blockchain technology as a promising technology for secure transactions. With the increasing popularity and interest in Blockchain, Ximedes wants to get hands-on experience by starting a proof-of-concept project for such implementation. The student is expected to already have knowledge of java, agile/scrum, micro-services and to be interested in Blockchain technology. Ximedes sees the following activities as part of the assignment:

  • Get a thorough understanding of Blockchain technology and the applications
  • Look into online projects as Ethereum en Blockstream
  • Look into Linux Hyperledger and Digital Asset Holding; as open-source platform for blockchain-applications. See also Multi-chain
  • Start with the development environment and the database
  • Implement a proof of concept application for closed payment platforms (https://www.ximedes.com/payments-applications/), all based on permissioned ledgers.

Company Name: Ximedes Software
Location: Haarlem, NL
Start date: Begining 2017
Duration: 9 months
Position: MSc thesis student

 

[CE2016-3] Philips Healthcare (NL) - Tools and techniques for transforming software to portable hardware 

Philips Healthcare is constantly looking for methods to improve the quality, life time, cost price and maintainability of its systems. At our department we are working on systems which visually assist and guide physicians during an intervention. The X-Ray system should be reliable and should deliver real time high quality images to the physician.

Currently we are studying tools and techniques to transform a C/C++ based algorithm to configurable hardware while maintaining portability. You might, amongst other subjects, work on an implementation with OpenCL on a configurable multicore system on an FPGA. Both hardware and software knowledge are required.

This study is part of the European ARTEMIS ALMARVI project (http://www.almarvi.eu/) and part of the results will be presented in the study. You should have a background, but a least a strong interest and willingness to learn in:

- (Embedded) computer architecture
- Pipelined software and hardware
- Multicore systems and programming
- OpenCL
- C/C++ in general
- High Level Synthesis
- Microcontroller programming
- FPGA design
- Image processing
- The English language, both spoken and written

Company Name: Philips Healthcare
Location: Best, NL
Start date: End 2016
Duration: 3-9 months
Position: Internship or MSc thesis student

 

[CE2016-2] Technolution (NL) - Resource-friendly fault-tolerant memory management unit for the RISC-V processor

RISC-V is a new instruction set architecture that has promising features for both low-end as high-end applications. Technolution built its own RISC-V core targeting safety critical or security critical applications. These applications require the core to withstand or detect errors due to single even upsets (SEUs). In order to make the entire path from the core to the memory safe for these errors, we would like to have an MMU implementation that can detect (and possibly correct) SEU errors. Furthermore, we would like to add the MMU also for low-end applications. Therefore, the core needs to be scalable in the amount of resources used. Possibly only memory protection is performed for low-end applications.

The assignment is develop a resource friendly MPU & MMU implementation that is protected for SEU errors. The MPU/MMU is written in VHDL and targeted for FPGAs. The research questions of this assignment that need to be answered are as follows.

- What mechanisms are available to implement an MMU that has SEU protection in the data and control logic? Can both the control and data path use the same mechanisms for SEU protection or are different mechanisms more appropriate?

- Which architectural optimizations can be done to optimize the resource usage for the MMU/MPU when targeting low-end applications?

Company Name: Technolution
Location: Gouda, NL
Start date: End 2016
Duration: 9 months
Position type: MSc project

 

[CE2016-1] Erasmus MC (NL) - Multi-FPGA Implementation of Artificial-Cerebellum Computational Model

Over the last decade, an increasing amount of effort is being spent on constructing and, then, simulating powerful brain models that can greatly help in unraveling the mysteries of the human brain (see for instance the EU flagship project: www.humanbrainproject.eu). Whereas these models are powerful and constantly come closer to the real brain functionality, however they are typically very computationally intensive, to the point that common platforms such as multicore CPUs fall short of reasonable execution times. We have thus turned to more powerful platforms, FPGAs. While FPGAs receive high marks when it comes to performance acceleration, nevertheless, their limited capacity is not sufficient for implementing large-scale brain simulations comprising (hundreds of) thousands neurons. The subject of this topic is to extend a currently implemented, biologically-accurate, simulation platform (comprising a single FPGA) to incorporate multiple FPGAs. If the inter-FPGA communication challenges are recognized and sufficiently dealt with, this extension is expected to double the achievable real-time brain simulation capabilities with every new FPGA on the stack. The platform is to be used for biophysically-meaningful simulations of Cerebellar microsections in the Neuroscience Department of the Erasmus MC, Rotterdam. The student is expected to analyze the original single-FPGA neural models, identify latency-sensitive sections and potential optimizations and, then, deploy (through use of suitable EDA tools, e.g. Compaan) the original application onto a multi-FPGA arrangement.

Company Name: Erasmus Medical Center
Location: Rotterdam, NL
Start date: 2016
Duration: 9 months
Position type: MSc project

 

[CE2015-2] Philips Healthcare (NL) - Multicore Implementation of Image Processing Algorithms 

Medical imaging devices are becoming more demanding, in terms of resolution, low latency, high throughput, etc. This sets ever increasing requirements on the computational systems used to process the information generated by these imaging devices. This project is concerned with designing and implementing cutting-edge image processing algorithms needed for high-end medical devices on heterogenous multicore platforms, such as CPU, FPGA and DSPs. The student will investigate the viability of these algorithms for multicore system and compare their performance between a number of system alternatives. Possible performance gains by running these algorithms on the rVEX processor will also be investigated.

This work is part of a collaboration between the TUDelft and Philips Healthcare within the ALMARVI European project. The results will be used to identify the best alternative platforms for next generation X-Ray imaging systems designed by Philips.

Company Name: Philips Healthcare
Location: Best, NL
Start date: Mid 2015
Duration: 3-9 months
Position: Internship or MSc thesis student

 

[CE2015-1] Philips Research (NL) - Acceleration and Optimization of Wide Area Ultrasound Communication Algorithms

New ultrasound communication/imaging techniques have enabled an increased throughput bandwidth for communication devices that require new efficient algorithms to ensure their appropriate processing. These algorithms need to be optimized and, in some cases, accelerated to meet their timing requirements. The student will combine knowledge about Digital Signal Processing (DSP), Matlab, as well as VHDL FPGA programming to create an appropriate ultrasound communication/imaging solution. The work is to be done within Philips Research in Eindhoven. Expected outcome includes the following:

  • Come up with suitable architectures for digital beam-forming for ultrasound in time and in the frequency domain
  • For the latter knowledge should be available for implementing FFTs, Hilbert transform (Cordic), FIR/IIR filters, ADC (SAR, sigma delta), CIC/SINC3 filters, I/Q demodulation, decimation/interpolation
  • Writing suitable test-vectors to perform verification on algorithmic level
  • Use the Matlab code to generate RTL-VHDL test benches and RTL-VHDL for the design blocks
  • Run synthesis on the RTL VHDL blocks to get an estimate on area/power/performance

Content and Goal: feasibility study of the concept and building a prototype based on existing ultrasound analog frontend + FPGA or DSP implementation

Student background: The student is expected to have knowledge of digital design, e.g. in application domains such as communications/imaging. Architectural design, having knowledge of MATLAB/VHDL programming and programmable DSPs or microprocessors (ARM, MSP). Having some knowledge on ADCs and analog circuit design or AMS could be a pre.

Company Name: Philips Research
Location: Eindhoven, NL
Start date: Mid 2015
Duration: 3-9 months
Position: Internship or MSc thesis student

 

[CE2014-4] Erasmus MC (NL) - Security in Body-Area Networks Using Heartbeat Monitoring

This topic is in the context of heartbeat-based security for implantable medical devices (IMDs). The time interval between heart beats contains a high degree of entropy, while it may be measured remarkably consistent throughout the human body. In other words, multiple entities on the same body may use this time interval to generate a nearly identical security key, showing minor disparities due to natural variations in the human body. Accordingly, secure communication is facilitated if the keys are "similar enough", evaluated by a key-classification scheme. In this topic, the student is expected to develop a key-classification scheme which adheres to the steep security requirements and tight constraints of IMDs.

Expected effort:
The student is expected to categorize various methods of heart-beat-based key-generation and key-classification schemes. Subsequently, these classification schemes are to be evaluated in terms of security and overheads (energy consumption, performance, etc). Based on this evaluation, the student is expected to design and evaluate a novel key-classification scheme tailored to heart-beat-based security.

Expected outcome:
A key-classification scheme which is suitable for heart-beat-based security in IMDs.

Prerequisites:
The student is expected to have a background in computer science, computer engineering or embedded systems and has a basic understanding of security concepts and low-power design.

Company Name: Erasmus Medical Center
Location: Rotterdam, NL
Start date: Start 2015
Duration: 9 months
Position type: MSc project

 

[CE2014-3] IBM (NL) - Detection of Security Vulnerabilities in Network Communication

IBM NL is a subsidiary of IBM based in the Netherlands, providing a diverse portfolio of computing solutions, services and products for large as well as small businesses in the fields of infrastructure, management, security, etc. This project is carried out in IBM Delft and focusses on research into the possibilities for improving the automated detection of security vulnerabilities in network communications setup of zSeries systems running z/OS, and sometimes z/VM with zLinux. Since these systems are often used in industries where information and its accuracy are of high value, attacks from legitimate users trying to exceed their authority as well as from outside can be expected.

Customers are worried about increased vulnerability as the knowledge and number of exploits available on the Internet increases. Concretely, under z/OS there exist a Policy Agent that can be used to define protection (like the type of encryption of authentication required) for network resources. There is however a need to verify the actual coverage of the policy over the network links that are really active. The network links are of two types: those implemented by (multiple) TCP/IP stacks, and those of SNA (Systems Network Architecture), with the added complexity of IP over SNA and SNA over IP being both possible. One of the troubles with analysing security is the limited understanding of the sensitivity of available resources. Some research into determining that to some extent in an automated way is warranted.

Company Name: IBM
Location: Delft, NL
Start date: End 2014
Duration: 9 months
Position type: MSc project

 

[CE2014-2] TOPIC (NL) - Facial recognition using Xilinx/Altera SoCs

In the domain of embedded processing, we see many different high-performance embedded processing platforms coming up. This varies from multicore processors via processors incorporating GPU and accelerator blocks to processors combining powerful CPUs with DSPs or FPGA fabric. Topic Embedded Systems is active in the area of embedded application development and very much focused on systems where software and FPGA functionality are overlapping. Think about video applications, algorithm implementation, data mining, etc. In this context, we want to explore the capabilities of the Altera and Xilinx SoCs, which both incorporate a dual-core Cortex A9 and a lot of FPGA fabric.

A typical application in our domain is facial recognition. The quality of facial recognition depends on the camera resolution, computational effort and applicable algorithm. Typically, the processor part of the SoC runs Linux. Part of the assignment is the implementation of a facial recognition algorithm that is able to recognize multiple faces in a video frame, track them over different frames and, when possible, identify the faces depending on a face matching database.

For the assignment you will use a USB connected camera as video source and an HDMI or a panel display for visualization. On top of Linux you will use e.g. Qt for visualization. The implementation of the facial recognition algorithm will make use of both the processor and the FPGA, exploring the capabilities the Xilinx or Altera SoC, the applicable tool flow and the available video processing functionality in terms of e.g. OpenCV, OpenCL, video tool kits, high-level synthesis (C to VHDL translation). The applicable SoC will be available as part of a Xilinx or Altera development platform. 

The result of the assignment will be a demonstrator, performing live facial recognition as well as a report on the investigated design routes, development flows and implementation experiences.

Company Name: TOPIC Embedded Systems
Location: Delft, The Netherlands
Start date: Start 2015
Duration: 9 months
Position: MSc student

 

[CE2014-1] MMM (NL) - Big Data Analyst

Big data applications are becoming ever more important to analyze the wealth of data being acquired from our environment. There is a lot of value to be gained by systematically organizing, classifying, and analyzing the collected unstructured data. For commercial organizations, this could translate to increased understanding of their respective market segments and identifying new product or market opportunities, which would translate to a financial benefit to those organizations.

You will work on investigating the required hardware and software infrastructure needed to build a big data analysis system. You will be working in a young and dynamic company to develop marketing solutions to big customers. The internship work will be carried out at MMM, Amsterdam (opposite to Amsterdam CS).

What do we expect from you?

  1. A data-driven, innovative, and hands-on attitude
  2. Analytical and critical thinking approach
  3. Experience with .NET
  4. Knowledge of data warehousing

Company Name: MMM (Make Marketing Magic)
Location: Amsterdam, The Netherlands
Start date: Mid 2014
Duration: 3 months
Position: internship student

 

[CE2013-5] ASML (NL) - Modeling and Performance Prediction for Multicore System Behavior

[CE2013-4] ASML (NL) - Parallelization and Acceleration of Motion Control Algorithms on Multicores

[CE2013-3] Escrypt (DE) - Security Hardware and Design-for-Testability Development for Automotive Applications

[CE2013-2] TNO (NL) - Model Characterization for the Design of Wireless Networks

[CE2013-1] TNO (NL) - Simulation Techniques for Distributed Adaptive Systems

[CE2012-8] IBM (NL) - Detection of Security Vulnerabilities in Network Communication

[CE2012-7] NVIDIA (US) - Bioinformatics Algorithms Parallelization on GPUs

[CE2012-6] Intel (NL) - Power Management for High-Performance Media Processors

[CE2012-5] Intel (NL) - Design Space Exploration for High-Performance Media Processors

[CE2012-4] TNO (NL) - Modeling and Simulation of Large-Scale Networks

[CE2012-3] TNO (NL) - System-wide Optimization of Distributed Dynamic Sub-systems

[CE2012-2] ST-Ericsson (FR) - Adaptive Voltage Scaling and IC Production Testing

[CE2012-1] Thomson Networks (FR) - Optimization of Parallel Video Processing Programs on Multicore/GPU Platforms

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