Publications Sorin Cotofana

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    2018

  1. Y. Jiang, N. Cucu Laurenciu, S.D. Cotofana, On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps1708_on_carving_basic_boolean_functions_on_graphene_nanoribbons.pdf (May 2018), IEEE International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence [Conference Paper]
  2. 2017

  3. M. Lefter, G.R. Voicu, T. Marconi, V. Savin, S.D. Cotofana, LDPC-Based Adaptive Multi-Error Correction for 3D Memories1641_ldpcbased_adaptive_multierror_correction_for_3d_memories.pdf (September 2017), 35th IEEE International Conference on Computer Design (ICCD 2017), 5-8 November 2017, Boston, USA [Conference Paper]
  4. N. Cucu Laurenciu, S.D. Cotofana, Haar-based Interconnect Coding for Energy Effective Medium/Long Range Data Transport1643_haarbased_interconnect_coding_for_energy_effective_medium.pdf (September 2017), 30th IEEE International System-on-Chip Conference (SOCC 2017), 5-8 September 2017, Munich, Germany [Conference Paper]
  5. M. Lefter, T. Marconi, G.R. Voicu, S.D. Cotofana, Low Cost Multi-Error Correction for 3D Polyhedral Memories1640_low_cost_multierror_correction_for_3d_polyhedral_memories.pdf (July 2017), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2017), 25-26 July 2017, Newporrt, USA [Conference Paper]
  6. N. Cucu Laurenciu, S.D. Cotofana, Fast and Accurate Workload-Level Neural Network Based IC Energy Consumption Estimation1642_fast_and_accurate_workloadlevel_neural_network_based_ic_en.pdf (June 2017), International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2017), 12-15 June 2017, Taormina, Italy [Conference Paper]
  7. 2016

  8. A. Makosiej, N. Gupta, N. Vakul, A. Vladimirescu, S.D. Cotofana, S. Mahapatra, A. Amara, C. Anghel, Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications (December 2016), Micro & Nano Letters, volume 11, doi:10.1049/mnl.2016.0442 [Journal Paper]
  9. J. Lee, F. Peper, S.D. Cotofana, M. Naruse, M. Ohtsu, T. Kawazoe, Y. Takahashi, T. Shimokawa, L. B. Kish, T. Kubota, Brownian Circuits: Designs1563_brownian_circuits_designs.pdf (December 2016), International Journal of Unconventional Computing (IJUC) , volume 12, issue 5-6 [Journal Paper]
  10. T. T. Nguyen-Ly, T. Gupta, M. Pezzin, V. Savin, D. Declercq, S.D. Cotofana, Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units (September 2016), 19th Euromicro Conference on Digital Systems Design (DSD 2016), 31 August - 2 September, Limassol, Cyprus, 10.1109/DSD.2016.33 [Conference Paper]
  11. C. Chen, Y. Fu, S.D. Cotofana, ”Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links”1547_towards_maximum_utilization_of_remained_bandwidth_in_def.pdf (August 2016), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , DOI: 10.1109/TCAD.2016.2570680 [Journal Paper]
  12. G.R. Voicu, S.D. Cotofana, High-performance, Cost-effective 3D Stacked Wide-Operand Adders1545_highperformance_costeffective_3d_stacked_wideoperand_ad.pdf (August 2016), IEEE Transactions on Emerging Topics in Computing, DOI: 10.1109/TETC.2016.2598290 [Journal Paper]
  13. N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, S.D. Cotofana, C. Anghel, TFET NDR Skewed Inverter based Sensing Method (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China, Best Concept Paper Award [Conference Paper]
  14. B. Yang, M. A. Quille, A. Amann, E. Popovici, S.D. Cotofana, A supply voltage-dependent variation aware reliability evaluation model (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China [Conference Paper]
  15. M. Enachescu, M. Lefter, G.R. Voicu, S.D. Cotofana, Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory (July 2016), IEEE Transactions on Emerging Topics in Computing, DOI: 10.1109/TETC.2016.2588725 [Journal Paper]
  16. N. Cucu Laurenciu, T. Gupta, V. Savin, S.D. Cotofana, Error Correction Code Protected Data Processing Units1579_error_correction_code_protected_data_processing_units.pdf (July 2016), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), 18-20 July 2016, Beijing, China [Conference Paper]
  17. B. Yang, S. Grandhi, C. Spagnol, E. Popovici, S.D. Cotofana, An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability (June 2016), 27th Irish Signals and Systems Conference (ISSC), 21-22 June 2016, Derry, Ireland [Conference Paper]
  18. 2015

  19. J. Chen, S.D. Cotofana, S. Grandhi, C. Spagnol, E. Popovici, Inverse Gaussian Distribution Based Timing Analysis of Sub-Threshold CMOS Circuits (December 2015), Microelectronics Reliability, volume 55, issue 12 [Journal Paper]
  20. A. Amaricai, N. Cucu Laurenciu, O. Boncalo, J. Chen, S. Nimara, V. Savin, S.D. Cotofana, Multi-Level Probabilistic Timing Error Reliability Analysis Using a Circuit Dependent Fault Map Generation (November 2015), XXX Conference on Design of Circuits and Integrated Systems (DCIS 2015), 25-27 November 2015, Estoril, Portugal [Conference Paper]
  21. A. Amaricai, V. Savin, O. Boncalo, N. Cucu Laurenciu, J. Chen, S.D. Cotofana, Timing Error Analysis of Flooded LDPC Decoders (November 2015), IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS), 2-4 November 2015, Tel-Aviv, Israel [Conference Paper]
  22. S. Grandhi, D. McCarthy, C. Spagnol, E. Popovici, S.D. Cotofana, ROST-C: Reliability Driven Optimisation and Synthesis Techniques for Combinational Circuits (October 2015), 33rd IEEE International Conference on Computer Design (ICCD 2015), 18-21 October 2015, New York, USA [Conference Paper]
  23. T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana, Transmission Channel Noise Aware Energy Effective LDPC Decoding1508_transmission_channel_noise_aware_energy_effective_ldpc_deco.pdf (October 2015), Chapter "VLSI-SoC: Internet of Things Foundations", Published by Springer International Publishing [Book Chapter]
  24. T. Marconi, S.D. Cotofana, Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding1486_dynamic_bitstream_length_scaling_energy_effective_stochasti.pdf (May 2015), ACM Great Lakes VLSI Symposium (GLSVLSI 2015), 20-22 May 2015, Pittsburgh, USA [Conference Paper]
  25. M. Lefter, G.R. Voicu, S.D. Cotofana, A Shared Polyhedral Cache for 3D Wide-I/O Multi-Core Computing Platforms1478_a_shared_polyhedral_cache_for_3d_wideio_multicore_comput.pdf (May 2015), IEEE International Symposium on Circuits and Systems (ISCAS 2015), 24-27 May 2015, Lisbon, Portugal [Conference Paper]
  26. J. Chen, A. Tisserand, E. Popovici, S.D. Cotofana, Asynchronous Charge Sharing Power Consistent Montgomery Multiplier (May 2015), 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 4-6 May 2015, Mountain View, Silicon Valley, California, USA [Conference Paper]
  27. N. Cucu Laurenciu, S.D. Cotofana, Low Cost and Energy, Thermal Noise Driven, Probability Modulated Random Number Generator1551_low_cost_and_energy_thermal_noise_driven_probability_modu.pdf (May 2015), IEEE International Symposium on Circuits and Systems (ISCAS 2015), 24-27 May 2015, Lisbon, Portugal [Conference Paper]
  28. C. Chen, M. Enachescu, S.D. Cotofana, Enabling Vertical Wormhole Switching in 3D NoC-Bus Hybrid Systems (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]
  29. A. Gheolbanoiu, L Petrica, S.D. Cotofana, Hybrid Adaptive Clock Management for FPGA Processor Acceleration (March 2015), 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France [Conference Paper]
  30. 2014

  31. C. Chen, S.D. Cotofana, Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs (December 2014), 7th International Workshop on Network on Chip Architectures (NoCArc 2014), 13-17 December 2014, Cambridge, UK [Conference Paper]
  32. H. Siewobr, K.A. Gbolagade, S.D. Cotofana, An efficient residue-to-binary converter for the new moduli set {2^{n/2} ± 1, 2^{2+1},2^n + 1} (December 2014), 4th International Symposium on Integrated Circuits (ISIC), 10-12 December 2014, Singapore [Conference Paper]
  33. T. Marconi, C. Spagnol, E. Popovici, S.D. Cotofana, Towards Energy Effective LDPC Decoding by Exploiting Channel Noise Variability1442_towards_energy_effective_ldpc_decoding_by_exploiting_channe.pdf (October 2014), 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2014), 6-8 October 2014, Playa del Carmen, Mexico [Conference Paper]
  34. S. Grandhi, C. Spagnol, J. Chen, E. Popovici, S.D. Cotofana, Reliability Aware Logic Synthesis through Rewriting (September 2014), 27th International IEEE SoC (System-on-Chip) Conference (SOCC), 2-5 September, Las Vegas, USA [Conference Paper]
  35. J. Chen, E. Popovici, A. Tisserand, S.D. Cotofana, Robust Sub-Powered Asynchronous Logic (September 2014), International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2014), 29 September - 1 October 2014, Palma de Mallorca, Spain [Conference Paper]
  36. N. Cucu Laurenciu, S.D. Cotofana, Probability Density Function Based Reliability Evaluation of Large-Scale ICs1585_probability_density_function_based_reliability_evaluation_o.pdf (July 2014), 10th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2014), 8-10 July 2014, Paris, France [Conference Paper]
  37. C. Chen, S.D. Cotofana, Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs1583_towards_an_effective_utilization_of_partially_defected_inte.pdf (July 2014), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), 9-11 July 2014, Tampa, USA [Conference Paper]
  38. M. Lefter, M. Enachescu, G.R. Voicu, S.D. Cotofana, Energy Effective 3D Stacked Hybrid NEMFET-CMOS Caches1582_energy_effective_3d_stacked_hybrid_nemfetcmos_caches.pdf (July 2014), 10th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2014), 8-10 July 2014, Paris, France [Conference Paper]
  39. J. Chen, C. Spagnol, S. Grandhi, E. Popovici, A. Amaricai, S.D. Cotofana, Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits1441_linear_compositional_delay_model_for_the_timing_analysis_of.pdf (July 2014), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), 9-11 July 2014, Tampa, USA [Conference Paper]
  40. N. Cucu Laurenciu, S.D. Cotofana, Critical Transistors Nexus Based Circuit-Level Aging Assessment and Prediction1358_critical_transistors_nexus_based_circuitlevel_aging_assess.pdf (June 2014), Journal of Parallel and Distributed Computing, volume 74, issue 6 [Journal Paper]
  41. Y. Wang, S.D. Cotofana, L. Fang, Analysis of the Impact of Spatial and Temporal Variation on the Stability of SRAM Arrays and Mitigation Technique Using Independent-Gate Devices1566_analysis_of_the_impact_of_spatial_and_temporal_variation_on.pdf (June 2014), Journal of Parallel and Distributed Computing, volume 74, issue 6 [Journal Paper]
  42. H. Pettenghi, S.D. Cotofana, L.A. Sousa, Efficient Method for Designing Modulo {2n ± k} Multipliers (January 2014), Journal of Circuits, Systems and Computers, volume 23, issue 1 [Journal Paper]
  43. 2013

  44. N. Aymerich, S.D. Cotofana, A. Rubio, Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell based Architectures1364_controlled_degradation_stochastic_resonance_in_adaptive_ave.pdf (November 2013), IEEE Transactions on Nanotechnology (TNANO) , volume 12, issue 6 [Journal Paper]
  45. N. Cucu Laurenciu, S.D. Cotofana, A Direct Measurement Scheme of Amalgamated Aging Effects with Novel On-Chip Sensor1359_a_direct_measurement_scheme_of_amalgamated_aging_effects_wi.pdf (October 2013), 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2013), 7-9 October 2013, Istanbul, Turkey [Conference Paper]
  46. N. Cucu Laurenciu, S.D. Cotofana, A Nonlinear Degradation Path Dependent End-of-Life Estimation Framework from Noisy Observations 1360_a_nonlinear_degradation_path_dependent_endoflife_estimati.pdf (September 2013), Microelectronics Reliability, volume 53, issue 9-11 [Journal Paper]
  47. C. Chen, S.D. Cotofana, An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs1386_an_effective_routing_algorithm_to_avoid_unnecessary_link_ab.pdf (September 2013), 16th Euromicro Conference on Digital System Design (DSD 2013), 4-6 September 2013, Santander, Spain [Conference Paper]
  48. C. Chen, S.D. Cotofana, A Low Cost Method to Tolerate Soft Errors in the NoC Router Control Plane1385_a_low_cost_method_to_tolerate_soft_errors_in_the_noc_router.pdf (September 2013), 26th Annual IEEE International SoC Conference (SOCC 2013), 4-6 September 2013, Erlangen, Germany [Conference Paper]
  49. G.R. Voicu, S.D. Cotofana, Towards Heterogenous 3D-Stacked Reliable Computing with von Neumann Multiplexing1369_towards_heterogenous_3dstacked_reliable_computing_with_von.pdf (July 2013), 9th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH 2013), July 15-17, 2013, New York City, USA [Conference Paper]
  50. C Bira, L Gugu, R Hobincu, V Codreanu, L Petrica, S.D. Cotofana, An Energy Effective SIMD Accelerator for Visual Pattern Matching1368_an_energy_effective_simd_accelerator_for_visual_pattern_mat.pdf (June 2013), 4th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2013), 13-14 June 2013, Edinburgh, Scotland [Conference Paper]
  51. G.R. Voicu, M. Lefter, M. Enachescu, S.D. Cotofana, 3D Stacked Wide-Operand Adders: A Case Study1586_3d_stacked_wideoperand_adders_a_case_study.pdf (June 2013), 24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington D.C., USA [Conference Paper]
  52. L Petrica, V Codreanu, S.D. Cotofana, VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling1367_vasile_a_reconfigurable_vector_architecture_for_instructio.pdf (June 2013), 12th IEEE Low Voltage Low Power Conference (FTFC 2013), 20-21 June 2013, Paris, France [Conference Paper]
  53. E.K. Bankas, K.A. Gbolagade, S.D. Cotofana, An Effective New CRT Based Reverse Converter for a Novel Moduli Set { 2^(2n+1)-1, 2^(2n+1), 2^(2n)-1 }1588_an_effective_new_crt_based_reverse_converter_for_a_novel_mo.PDF (June 2013), 24th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington D.C., USA [Conference Paper]
  54. Y. Wang, S.D. Cotofana, L. Fang, Lifetime Reliability Assessment with Aging Information from Low-Level Sensors1591_lifetime_reliability_assessment_with_aging_information_from.pdf (May 2013), Great Lakes Symposium on VLSI (GLSVLSI 2013 ), 2-3 May 2013, Paris, France [Conference Paper]
  55. M. Enachescu, M. Lefter, A. Bazigos, A. Ionescu, S.D. Cotofana, Ultra Low Power NEMFET Based Logic1589_ultra_low_power_nemfet_based_logic.pdf (May 2013), IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China [Conference Paper]
  56. M. Lefter, G.R. Voicu, M. Taouil, M. Enachescu, S. Hamdioui, S.D. Cotofana, Is TSV-based 3D Integration Suitable for Inter-die Memory Repair?1328_is_tsvbased_3d_integration_suitable_for_interdie_memory_r.pdf (March 2013), Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France [Conference Paper]
  57. 2012

  58. N. Cucu Laurenciu, S.D. Cotofana, Context Aware Slope Based Transistor-Level Aging Model1318_context_aware_slope_based_transistorlevel_aging_model.pdf (October 2012), Microelectronics Reliability, volume 52, issue 9-10 [Journal Paper]
  59. A.T. Nelson, A.M. Molnos, A. Beyranvand Nejad, D. Mirzoyan, S.D. Cotofana, K.G.W. Goossens, Embedded Computer Architecture Laboratory: A Hands-on Experience Programming Embedded Systems with Resource and Energy Constraints1315_embedded_computer_architecture_laboratory_a_handson_exper.pdf (October 2012), Workshop on Embedded and Cyber-Physical Systems Education (WESE 2012), 11 October 2012, Tampere, Finland [Conference Paper]
  60. G.R. Voicu, M. Enachescu, S.D. Cotofana, A 3D Stacked High Performance Scalable Architecture for 3D Fourier Transform1592_a_3d_stacked_high_performance_scalable_architecture_for_3d.pdf (September 2012), 30th IEEE International Conference on Computer Design (ICCD 2012), 30 September - 3 October 2012, Montreal, Canada [Conference Paper]
  61. Y. Wang, M. Enachescu, S.D. Cotofana, L. Fang, Variation tolerant on-chip degradation sensors for dynamic reliability management systems1310_variation_tolerant_onchip_degradation_sensors_for_dynamic.pdf (September 2012), Microelectronics Reliability, volume 52, issue 9-10 [Journal Paper]
  62. N. Aymerich, S.D. Cotofana, A. Rubio, Degradation Stochastic Resonance (DSR) in AD-AVG Architectures1327_degradation_stochastic_resonance_dsr_in_adavg_architectu.pdf (August 2012), 12th IEEE Conference on Nanotechnology (IEEE NANO 2012), 20-23 August 2012, Birmingham, UK, Best PhD Student Paper Award [Conference Paper]
  63. Y. Wang, S.D. Cotofana, L. Fang, Statistical Reliability Analysis of NBTI Impact on FinFET SRAMs and Mitigation Technique Using Independent-Gate Devices1294_statistical_reliability_analysis_of_nbti_impact_on_finfet_s.pdf (July 2012), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands [Conference Paper]
  64. N. Aymerich, S.D. Cotofana, A. Rubio, Adaptive Fault-Tolerant Architecture for Unreliable Technologies with Heterogenous Variability1326_adaptive_faulttolerant_architecture_for_unreliable_technol.pdf (July 2012), IEEE Transactions on Nanotechnology (TNANO) , volume 11, issue 4 [Journal Paper]
  65. N. Cucu Laurenciu, S.D. Cotofana, A Markovian, Variation-Aware Circuit-Level Aging Model 1317_a_markovian_variationaware_circuitlevel_aging_model.pdf (July 2012), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands [Conference Paper]
  66. S. Safiruddin, F. Peper, S.D. Cotofana, Stigmergic Search with Single Electron Tunneling Technology based Memory Enhanced Hubs1309_stigmergic_search_with_single_electron_tunneling_technology.pdf (July 2012), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands, Best PhD Student Paper Award [Conference Paper]
  67. S. Safiruddin, M. Lefter, D. Borodin, G.R. Voicu, S.D. Cotofana, Zero-Performance-Overhead Online Fault Detection and Diagnosis in 3D Stacked Integrated Circuits1308_zeroperformanceoverhead_online_fault_detection_and_diagno.pdf (July 2012), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012), 4-6 July 2012, Amsterdam, The Netherlands [Conference Paper]
  68. M. Enachescu, G.R. Voicu, S.D. Cotofana, Is the Road Towards "Zero-Energy" Paved with NEMFET-based Power Management?141_is_the_road_towards_zeroenergy_paved_with_nemfetbased_po.pdf (May 2012), IEEE International Symposium on Circuits and Systems (ISCAS 2012), 20-23 May 2012, Seoul, Korea, Finalist for Best Paper Award for PhD Students [Conference Paper]
  69. C. Chen, Ye Lu, S.D. Cotofana, A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip139_a_novel_flit_serialization_strategy_to_utilize_partially_fau.pdf (May 2012), 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2012), 9-11 May 2012, Lyngby, Denmark [Conference Paper]
  70. A.M. Molnos, A. Beyranvand Nejad, B.T. Nguyen, S.D. Cotofana, K.G.W. Goossens, Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms138_decoupled_inter_and_intraapplication_scheduling_for_compos.pdf (May 2012), 5th Workshop on Mapping of Applications to MPSoCs & 15th International Workshop on Software and Compilers for Embedded Systems (Map2MPSoC/SCOPES 2012), 15-16 May 2012, St. Goar, Germany [Conference Paper]
  71. S. Safiruddin, D. Borodin, M. Lefter, G.R. Voicu, S.D. Cotofana, Is 3D Integration The Way to Future Dependable Computing Platforms?1307_is_3d_integration_the_way_to_future_dependable_computing_pl.pdf (May 2012), 13th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM 2012), 24-26 May 2012, Brasov, Romania [Conference Paper]
  72. 2011

  73. M. Enachescu, G.R. Voicu, S.D. Cotofana, Leakage-enhanced 3D-Stacked NEMFET-based Power Management Architecture for Autonomous Sensors Systems107_leakageenhanced_3dstacked_nemfetbased_power_management_ar.pdf (October 2011), 15th International Conference on System Theory, Control and Computing (ICSTCC 2011), 14-16 October 2011, Sinaia, Romania, Best Paper Award for PhD Students [Conference Paper]
  74. K.A. Gbolagade, G.R. Voicu, S.D. Cotofana, An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1}16_an_efficient_fpga_design_of_residuetobinary_converter_for_t.pdf (August 2011), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI) , volume 19, issue 8 [Journal Paper]
  75. D. Borodin, W. Siauw, S.D. Cotofana, Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems42_functional_unit_sharing_between_stacked_processors_in_3d_inte.pdf (July 2011), International Conference on Embedded Computer Systems: Architectures, Models, and Simulations (SAMOS XI), 18-21 July 2011, Samos, Greece [Conference Paper]
  76. G.R. Voicu, M. Enachescu, S.D. Cotofana, Towards "Zero-energy" using NEMFET-based Power Management for 3D Hybrid Stacked ICs56_towards_zeroenergy_using_nemfetbased_power_management_for.pdf (June 2011), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), 8-9 June 2011, San Diego, USA [Conference Paper]
  77. Y. Wang, S.D. Cotofana, A Unified Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits52_a_unied_aging_model_of_nbti_and_hci_degradation_towards_li.pdf (June 2011), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), 8-9 June 2011, San Diego, USA [Conference Paper]
  78. D. Andrade, A. Rubio, A. Calomarde, S.D. Cotofana, Analysis of delay mismatching of digital circuits caused by common environmental fluctuations (May 2011), IEEE International Symposium on Circuits and Systems (ISCAS 2011), 15-18 May, 2011, Rio de Janeiro, Brazil [Conference Paper]
  79. J.A. Ambrose, A.M. Molnos, A.T. Nelson, S.D. Cotofana, K.G.W. Goossens, B.H.H. Juurlink, Composable Local Memory Organisation for Streaming Applications on Embedded MPSoCs65_composable_local_memory_organisation_for_streaming_applicatio.pdf (May 2011), ACM International Conference on Computing Frontiers (CF 2011), 3-5 May 2011, Ischia, Italy [Conference Paper]
  80. 2010

  81. M. Enachescu, G.R. Voicu, S.D. Cotofana, Advanced NEMS-based Power Management for 3D Stacked Integrated Circuits243_advanced_nemsbased_power_management_for_3d_stacked_integrat.pdf (December 2010), International Conference on Energy Aware Computing (ICEAC 2010), 16-18 December 2010, Cairo, Egypt [Conference Paper]
  82. Y. Wang, S.D. Cotofana, A Novel Virtual Age Reliability Model for Time-toFailure Prediction264_a_novel_virtual_age_reliability_model_for_timetofailure_pre.pdf (October 2010), IEEE International Integrated Reliability Workshop Final Report (IRW 2010), 17-21 October 2010, South Lake Tahoe, USA [Conference Paper]
  83. S. Timarchi, M. Fazlali, S.D. Cotofana, A Unified Addition Structure for Moduli Set {2n-1, 2n, 2n+1} based on a Novel RNS Representation263_a_unified_addition_structure_for_moduli_set_2n1_2n_2n1.pdf (October 2010), 28th International Conference on Computer Design (ICCD 2010), 3-6 October 2010, Amsterdam, The Netherlands [Conference Paper]
  84. K.A. Gbolagade, G.R. Voicu, S.D. Cotofana, An Efficient FPGA Design of Reverse Converter for the Moduli Set {2n+2,2n+1,2n}167_an_efficient_fpga_design_of_reverse_converter_for_the_moduli.pdf (July 2010), 6th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2010), 11-17 July 2010, Terrassa, Spain [Conference Paper]
  85. K.A. Gbolagade, G.R. Voicu, S.D. Cotofana, Memoryless RNS-to-Binary Converters for the moduli set {2n+1-1,2n,2n-1}166_memoryless_rnstobinary_converters_for_the_moduli_set_2n1.pdf (July 2010), 21st IEEE International Conference on Application Specific Systems Architectures, and Processors (ASAP 2010), 7-9 July 2010, Rennes, France [Conference Paper]
  86. K.A. Gbolagade, R. Chaves, L.A. Sousa, S.D. Cotofana, An Improved Reverse Converter for the {2^{2n+1}-1, 2^{n}, 2^{n}-1} Moduli Set176_an_improved_reverse_converter_for_the_22n11_2n_2.pdf (June 2010), IEEE International Symposium on Circuits and Systems (ISCAS 2010), 30 May - 2 June 2010, Paris, France [Conference Paper]
  87. A.M. Molnos, J.A. Ambrose, A.T. Nelson, R.A. Stefan, K.G.W. Goossens, S.D. Cotofana, A Composable, Energy-Managed, Real-Time MPSOC Platform192_a_composable_energymanaged_realtime_mpsoc_platform.pdf (May 2010), 12th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM 2010), 20-22 May 2010, Brasov, Romania [Conference Paper]
  88. 2009

  89. K.A. Gbolagade, S.D. Cotofana, A Reverse Converter for the New 4-Moduli Set {2n+3,2n+2,2n+1,2n}379_a_reverse_converter_for_the_new_4moduli_set_2n32n22n1.pdf (December 2009), 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS09), 13-19 December 2009, Yasmine Hammamet, Tunesia [Conference Paper]
  90. K.A. Gbolagade, R. Chaves, L.A. Sousa, S.D. Cotofana, Residue-to-Binary Converters for the Moduli Set {2^{2n+1}-1, 2^{2n}, 2^{n}-1}378_residuetobinary_converters_for_the_moduli_set_22n11.pdf (December 2009), 2nd International Conference On Adaptive Science & Technology (ICAST09), 14-16 December 2009, Accra, Ghana [Conference Paper]
  91. M. Enachescu, A.J. van Genderen, S.D. Cotofana, A. Ionescu, D. Tsamados, Can SG-FET Replace FET In Sleep Mode Circuits?410_can_sgfet_replace_fet_in_sleep_mode_circuits.pdf (October 2009), 4th International ICST Conference on Nano-Networks (NANO-NET 2009), 18-20 October 2009, Luzern, Switzerland [Conference Paper]
  92. M. Enachescu, A.J. van Genderen, S.D. Cotofana, Suspended Gate Field Effect Transistor Based Power Management - A 32-Bit Adder Case Study408_suspended_gate_field_effect_transistor_based_power_managemen.PDF (October 2009), International Semiconductor Conference (CAS 2009), 12-14 October 2009, Sinaia, Romania, Honorific Mention [Conference Paper]
  93. K.A. Gbolagade, S.D. Cotofana, Residue-to-Decimal Converters for Moduli Sets with Common Factors294_residuetodecimal_converters_for_moduli_sets_with_common_fa.pdf (August 2009), 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009), 2-5 August 2009, Cancun, Mexico [Conference Paper]
  94. I.O. Agbo, S. Safiruddin, S.D. Cotofana, Implementable Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology321_implementable_building_blocks_for_fluctuation_based_calculat.pdf (July 2009), 9th IEEE Conference on Nanotechnology (IEEE-NANO 2009), 26-30 July 2009, Genoa, Italy [Conference Paper]
  95. B. Kuiper, S.D. Cotofana, Adaptive Clock Scheduling for Pipelined Structures320_adaptive_clock_scheduling_for_pipelined_structures.pdf (July 2009), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009), 30-31 July 2009, San Fransisco, USA [Conference Paper]
  96. K.A. Gbolagade, S.D. Cotofana, An O(n) Residue Number System to Mixed Radix Conversion Technique334_an_on_residue_number_system_to_mixed_radix_conversion_tech.pdf (May 2009), IEEE International Symposium on Circuits and Systems (ISCAS 2009), 24-27 May 2009, Taipei, Taiwan [Conference Paper]
  97. N.Z.B. Haron, S. Hamdioui, S.D. Cotofana, Emerging Non-CMOS Nanoelectronic Devices - What Are They?412_emerging_noncmos_nanoelectronic_devices__what_are_they.pdf (January 2009), 4th IEEE International Conference of Nano/Micro Engineered & Molecular Systems (IEEE-NEMS 2009), 5-8 January 2009, Shenzhen, China [Conference Paper]
  98. 2008

  99. K.A. Gbolagade, S.D. Cotofana, MRC Technique for RNS to Decimal Conversion Using the Moduli Set {2n + 2, 2n + 1, 2n}528_mrc_technique_for_rns_to_decimal_conversion_using_the_moduli.pdf (November 2008), 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008, Veldhoven, The Netherlands [Conference Paper]
  100. K.A. Gbolagade, S.D. Cotofana, An Efficient RNS to Binary Converter Using the Moduli Set {2n+1, 2n, 2n-1}521_an_efficient_rns_to_binary_converter_using_the_moduli_set_2.pdf (November 2008), XXIII Conference on Design of Circuits and Integrated Systems (DCIS 2008), 12-14 November 2008, Grenoble, France [Conference Paper]
  101. K.A. Gbolagade, S.D. Cotofana, Generalized Matrix Method for Efficient Residue to Decimal Conversion506_generalized_matrix_method_for_efficient_residue_to_decimal_c.pdf (November 2008), IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008), 30 November - 3 December 2008, Macao, China [Conference Paper]
  102. A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven, Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors551_compositional_dynamic_cache_management_for_embedded_chip_mu.pdf (October 2008), Journal of Signal Processing Systems (JSPS) , volume 57, issue 2 [Journal Paper]
  103. K.A. Gbolagade, S.D. Cotofana, A residue to Binary Converter for the {2n+2,2n+1,2n} Moduli Set540_a_residue_to_binary_converter_for_the_2n22n12n_moduli.pdf (October 2008), 42nd Asilomar Conference on Signals, Systems and Computers, 26-29 October 2008, Pacific Grove, USA [Conference Paper]
  104. R.A. Stefan, S.D. Cotofana, Bitstream Compression Techniques for Virtex 4 FPGAs426_bitstream_compression_techniques_for_virtex_4_fpgas.pdf (September 2008), 18th International Conference on Field Programmable Logic and Applications (FPL 2008), 8-10 September 2008, Heidelberg, Germany [Conference Paper]
  105. S. Safiruddin, S.D. Cotofana, F. Peper, J. Lee, Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology444_building_blocks_for_fluctuation_based_calculation_in_single.pdf (August 2008), 8th IEEE Conference on Nanothechnology (NANO 2008), 18-21 August 2008, Arlington, USA [Conference Paper]
  106. K.A. Gbolagade, S.D. Cotofana, Residue Number System Operands to Decimal Conversion for 3-Moduli Sets437_residue_number_system_operands_to_decimal_conversion_for_3m.pdf (August 2008), 51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2008), 10-13 August 2008, Knoxville, USA [Conference Paper]
  107. B.H.H. Juurlink, I. Antochi, D. Crisu, S.D. Cotofana, GRAAL: A Framework for Low-Power 3D Graphics Accelerators (July 2008), IEEE Computer Graphics and Applications (CGA) , volume 28, issue 4 [Journal Paper]
  108. S. Safiruddin, S.D. Cotofana, F. Peper, Single Electron Tunneling Delay Insensitive and Fluctuation Based Computation Paradigms and Circuits472_single_electron_tunneling_delay_insensitive_and_fluctuation.pdf (June 2008), IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008), 12-13 June 2008, Anaheim, USA [Conference Paper]
  109. A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, Compositional, dynamic cache management for embedded chip multiprocessors502_compositional_dynamic_cache_management_for_embedded_chip_mu.pdf (March 2008), Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany [Conference Paper]
  110. F. Martorell, S.D. Cotofana, A. Rubio, An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates556_an_analysis_of_internal_parameter_variations_effects_on_nano.pdf (January 2008), IEEE Transactions on Nanotechnology (TNANO) , volume 7, issue 1 [Journal Paper]
  111. 2007

  112. S.D. Cotofana, On Effective Computation with Single Electron Devices690_on_effective_computation_with_single_electron_devices.pdf (November 2007), 22nd Conference on Design of Circuits and Integrated Systems (DCIS 2007), 21-23 November 2007, Sevilla, Spain [Conference Paper]
  113. D. Lampridis, S.D. Cotofana, High speed reconfigurable computation for electronic instrumentation in space applications677_high_speed_reconfigurable_computation_for_electronic_instrum.pdf (November 2007), 18th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2007), 29-30 November 2007, Veldhoven, The Netherlands [Conference Paper]
  114. F. Martorell, S.D. Cotofana, A. Rubio, Manufacturability Issues of Redundant Nanogates694_manufacturability_issues_of_redundant_nanogates.pdf (October 2007), International Semiconductor Conference (CAS 2007), 15-17 October 2007, Sinaia, Romania [Conference Paper]
  115. K.L.M. Bertels, S.D. Cotofana, G.N. Gaydadjiev, K.G.W. Goossens, S. Hamdioui, B.H.H. Juurlink, A.J. van Genderen, S. Wong, The Future of Computing, essays in memory of Stamatis Vassiliadis (September 2007), Published by Computer Engineering Laboratory, TU Delft [Book]
  116. A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors580_static_cache_partitioning_robustness_analysis_for_embedded_o.pdf (August 2007), Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC) , volume 1 [Journal Paper]
  117. F. Martorell, S.D. Cotofana, A. Rubio, Fault Tolerant Structures for Nanoscale Gates579_fault_tolerant_structures_for_nanoscale_gates.pdf (August 2007), 7th IEEE International Conference on Nanotechnology (IEEE-NANO 2007), 2-5 August 2007, Hong Kong, China [Conference Paper]
  118. S. Safiruddin, S.D. Cotofana, Building Blocks for Delay-Insensitive Circuits using Single Electron Tunneling Devices578_building_blocks_for_delayinsensitive_circuits_using_single.pdf (August 2007), 7th IEEE International Conference on Nanotechnology (IEEE-NANO 2007), 2-5 August 2007, Hong Kong, China [Conference Paper]
  119. C.H. Meenderinck, S.D. Cotofana, Computing Division Using Single-Electron Tunneling Technology597_computing_division_using_singleelectron_tunneling_technolog.pdf (July 2007), IEEE Transactions on Nanotechnology (TNANO) , volume 6, issue 4 [Journal Paper]
  120. C.H. Meenderinck, S.D. Cotofana, An Analysis of Basic Structures for Effective Computation in Single Electron Tunneling Technology637_an_analysis_of_basic_structures_for_effective_computation_in.pdf (March 2007), Romanian Journal of Information Science and Technology (ROMJIST) , volume 10, issue 1 [Journal Paper]
  121. 2006

  122. I. Koryfidis, S.D. Cotofana, A Power Aware HW/SW Partitioning for a DVB-H Receiver Module787_a_power_aware_hwsw_partitioning_for_a_dvbh_receiver_module.pdf (November 2006), 17th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006), 23-24 November 2006, Veldhoven, The Netherlands [Conference Paper]
  123. T. Niculiu, S.D. Cotofana, Hierarchical Continuous Intelligence Simulation (September 2006), Romanian Journal of Information Science and Technology (ROMJIST) [Journal Paper]
  124. D. Milosavljevic, S.D. Cotofana, A Method to Analyze the Fault Tolerance of Molecular Quantum-Dot Cellular Automata Systems706_a_method_to_analyze_the_fault_tolerance_of_molecular_quantum.pdf (September 2006), International Semiconductor Conference (CAS 2006), 27-29 September 2006, Sinaia, Romania [Conference Paper]
  125. C.H. Meenderinck, S.D. Cotofana, Basic Building Blocks for Effective Single Electron Tunneling Technology Based Computation705_basic_building_blocks_for_effective_single_electron_tunnelin.pdf (September 2006), International Semiconductor Conference (CAS 2006), 27-29 September 2006, Sinaia, Romania [Conference Paper]
  126. A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven, Throughput Optimization via Cache Partitioning for Embedded Multiprocessors722_throughput_optimization_via_cache_partitioning_for_embedded.pdf (July 2006), International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), 17-20 July 2006, Samos, Greece [Conference Paper]
  127. C.H. Meenderinck, S.D. Cotofana, High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology721_highradix_addition_and_multiplication_in_the_electron_count.pdf (July 2006), 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2006), 17-20 July 2006, Samos, Greece [Conference Paper]
  128. C.H. Meenderinck, S.D. Cotofana, Computing Division in the Electron Counting Paradigm using Single Electron Tunneling Technology720_computing_division_in_the_electron_counting_paradigm_using_s.pdf (July 2006), 6th IEEE Conference on Nanotechnology (IEEE-NANO 2006), 17-20 July 2006, Cincinnati, USA [Conference Paper]
  129. A.M. Molnos, S.D. Cotofana, M.J.M. Heijligers, J.T.J. van Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On­Chip Multi­Processors745_static_cache_partitioning_robustness_analysis_for_embedded_o.pdf (May 2006), 3rd International Conference on Computing Frontiers (CF 2006), 3-5 May 2006, Ischia, Italy [Conference Paper]
  130. C.H. Meenderinck, S.D. Cotofana, Electron Counting based High-Radix Multiplication in Single Electron Tunneling Technology746_electron_counting_based_highradix_multiplication_in_single.pdf (May 2006), International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Kos, Greece [Conference Paper]
  131. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, Compositional, efficient caches for a chip multi-processor759_compositional_efficient_caches_for_a_chip_multiprocessor.pdf (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany [Conference Paper]
  132. 2005

  133. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, Inter-task sharing data and instructions in cache with enabling compositionality in parallel embedded systems898_intertask_sharing_data_and_instructions_in_cache_with_enabl.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]
  134. L. Zhang, S.D. Cotofana, An Input Weights Aware Synthesis Tool for Threshold Logic Networks873_an_input_weights_aware_synthesis_tool_for_threshold_logic_ne.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]
  135. K.C. Li, M.D. Padure, S.D. Cotofana, neuronMOS enhanced Differential Current-Switch Threshold Logic Gates872_neuronmos_enhanced_differential_currentswitch_threshold_log.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]
  136. C.H. Meenderinck, S.D. Cotofana, Periodic Symmetric Functions and Addition Related Arithmetic Operations in Single Electron Tunneling Technology867_periodic_symmetric_functions_and_addition_related_arithmetic.pdf (November 2005), 16th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005), 17-18 November 2005, Veldhoven, The Netherlands [Conference Paper]
  137. C.H. Meenderinck, S.D. Cotofana, Computing Periodic Symmetric Functions in Single Electron Tunneling Technology891_computing_periodic_symmetric_functions_in_single_electron_tu.pdf (October 2005), International Semiconductor Conference (CAS 2005), 3-5 October 2005, Sinaia, Romania, Best Paper Award [Conference Paper]
  138. S.D. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio, CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures829_conan__a_design_exploration_framework_for_reliable_nanoele.pdf (July 2005), 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece [Conference Paper]
  139. C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana, High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology828_high_radix_addition_via_conditional_charge_transport_in_sing.pdf (July 2005), 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece [Conference Paper]
  140. C.H. Meenderinck, C.R. Lageweg, S.D. Cotofana, Design Methodology for Single Electron Based Building Blocks825_design_methodology_for_single_electron_based_building_blocks.pdf (July 2005), 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan [Conference Paper]
  141. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Buffer Design Trade-Offs for Single Electron Logic Gates824_buffer_design_tradeoffs_for_single_electron_logic_gates.pdf (July 2005), 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 11-15 July 2005, Nagoya, Japan, Best Paper Award [Conference Paper]
  142. M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis, L.J. Visser, IEEE-Compliant IDCT on FPGA-Augmented TriMedia853_ieeecompliant_idct_on_fpgaaugmented_trimedia.pdf (March 2005), Journal of Signal Processing Systems (JSPS) , volume 39, issue 3 [Journal Paper]
  143. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, Compositional memory systems for multimedia communicating tasks856_compositional_memory_systems_for_multimedia_communicating_ta.pdf (March 2005), Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany [Conference Paper]
  144. S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, Addition Related Arithmetic Operations via Controlled Transport of Charge854_addition_related_arithmetic_operations_via_controlled_transp.pdf (March 2005), IEEE Transactions on Computers (TC) , volume 54, issue 3 [Journal Paper]
  145. 2004

  146. C. Hu, S.D. Cotofana, J. Jianfei, Single-Electron Tunneling Transistor Implementation of Periodic Symmetric Functions976_singleelectron_tunneling_transistor_implementation_of_perio.pdf (November 2004), IEEE Transactions on Circuits and Systems Part II: Express Briefs (TCAS) , volume 51, issue 11 [Journal Paper]
  147. C. Hu, S.D. Cotofana, J. Jianfei, Q. Cai, Analog-to-Digital Converter Based on Single-Electron Tunneling Transistors968_analogtodigital_converter_based_on_singleelectron_tunneli.pdf (November 2004), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI) , volume 12, issue 11 [Journal Paper]
  148. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, Cache Partitioning Options for Compositional Multimedia Applications987_cache_partitioning_options_for_compositional_multimedia_appl.pdf (November 2004), 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands [Conference Paper]
  149. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, 3D Graphics Tile-Based Systolic Scan-Conversion985_3d_graphics_tilebased_systolic_scanconversion.pdf (November 2004), 38th Asilomar Conference on Signals, Systems and Computers (Asilomar 2004), 7-10 November 2004, Pacific Grove, USA [Conference Paper]
  150. A.J. van Genderen, S.D. Cotofana, G. de Graaf, A. Kaichouhi, J. Liedorp, R. Nouta, M.A.P. Pertijs, C.J.M. Verhoeven, A CMOS Semi-Custom Chip for Mixed Signal Designs981_a_cmos_semicustom_chip_for_mixed_signal_designs.pdf (November 2004), 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands [Conference Paper]
  151. L. Huang, D. Crisu, S.D. Cotofana, Heuristic Algorithms for Primitive Traversal Acceleration in Tile-Based Rasterizers979_heuristic_algorithms_for_primitive_traversal_acceleration_in.pdf (November 2004), 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands [Conference Paper]
  152. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, Efficient Hardware for Tile-Based Rasterization978_efficient_hardware_for_tilebased_rasterization.pdf (November 2004), 15th Annual Workshop on Circuits, Systems and Signal Processing (ProRisc 2004), 25-26 November 2004, Veldhoven, The Netherlands [Conference Paper]
  153. T. Niculiu, A. Manolescu, S.D. Cotofana, Looking for Intelligent Reconfigurable Simulation994_looking_for_intelligent_reconfigurable_simulation.pdf (October 2004), European Simulation and Modelling Conference (ESMc 2004), 25-27 October 2004, Paris, France [Conference Paper]
  154. S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, On Effective Computation with Nanodevices: A single Electron Tunneling Case Study990_on_effective_computation_with_nanodevices_a_single_electron.pdf (October 2004), International Semiconductor Conference (CAS 2004), 4-6 October 2004, Sinaia, Romania, Invited Paper [Conference Paper]
  155. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, Determining a coverage mask for a pixel (October 2004), filed in USA [Patent]
  156. C. Hu, S.D. Cotofana, J. Jianfei, Digital to analogue converter based on single-electron tunnelling transistor995_digital_to_analogue_converter_based_on_singleelectron_tunne.pdf (October 2004), IEE Proceedings - Circuits, Devices and Systems, volume 151, issue 5 [Journal Paper]
  157. P. Celinski, D. Abbott, S.D. Cotofana, Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic903_delay_evaluation_of_high_speed_datapath_circuits_based_on_t.pdf (September 2004), 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), 15-17 September 2004, Santorini, Greece [Conference Paper]
  158. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Binary Addition based on Single Electron Tunneling Devices904_binary_addition_based_on_single_electron_tunneling_devices.pdf (August 2004), 4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany [Conference Paper]
  159. J. Cheng, C. Hu, S.D. Cotofana, J. Jianfei, SPICE Implementation of a Compact Single Electron Tunneling Transistor Model906_spice_implementation_of_a_compact_single_electron_tunneling.pdf (August 2004), 4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany [Conference Paper]
  160. C. Hu, S.D. Cotofana, J. Jianfei, Compact Current and Current Noise Models for Single-Electron Tunneling Transistors905_compact_current_and_current_noise_models_for_singleelectron.pdf (August 2004), 4th IEEE Conference on Nanotechnology (IEEE-NANO 2004), 16-19 August 2004, Munich, Germany [Conference Paper]
  161. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, Logic-Enhanced Memory for 3D Graphics Tile-Based Rasterizers923_logicenhanced_memory_for_3d_graphics_tilebased_rasterizers.pdf (July 2004), 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), 25-28 July 2004, Hiroshima, Japan [Conference Paper]
  162. T. Niculiu, S.D. Cotofana, Hierarchical Inteligent Simulation (July 2004), 16th International Conference on Systems Research, Informatics and Cybernetics, 28 July - 4 August 2004, Baden-Baden, Germany [Conference Paper]
  163. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs977_highlevel_energy_estimation_for_armbased_socs.pdf (July 2004), 4th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2004), 19-21 July 2004, Samos, Greece [Conference Paper]
  164. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, Efficient Hardware for Antialiasing Coverage Mask Generation928_efficient_hardware_for_antialiasing_coverage_mask_generation.pdf (June 2004), Computer Graphics International Conference (CGI 2004), 16-19 June 2004, Crete, Greece [Conference Paper]
  165. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single Electron Encoded Latches and Flip-Flops927_single_electron_encoded_latches_and_flipflops.pdf (June 2004), IEEE Transactions on Nanotechnology (TNANO) , volume 3, issue 2 [Journal Paper]
  166. M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, L.J. Visser, Pel Reconstruction on FPGA-Augmented TriMedia926_pel_reconstruction_on_fpgaaugmented_trimedia.pdf (June 2004), IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI) , volume 12, issue 6 [Journal Paper]
  167. D. Crisu, S. Vassiliadis, S.D. Cotofana, P. Liuha, Low Cost and Latency Embedded 3D Graphics Reciprocation932_low_cost_and_latency_embedded_3d_graphics_reciprocation.pdf (May 2004), IEEE International Symposium on Circuits and Systems (ISCAS 2004), 23-26 May 2004, Vancouver, Canada [Conference Paper]
  168. C. Hu, S.D. Cotofana, J. Jianfei, Analysis of Analog to Digital Converter Based on Single Electron Tuneling Transistors934_analysis_of_analog_to_digital_converter_based_on_single_elec.pdf (May 2004), IEEE International Symposium on Circuits and Systems (ISCAS 2004), 23-26 May 2004, Vancouver, Canada [Conference Paper]
  169. S. Wong, S. Vassiliadis, S.D. Cotofana, Embedded Processors: Characteristics and Trends933_embedded_processors_characteristics_and_trends.pdf (May 2004), CE technical report [Technical Report]
  170. T. Niculiu, M. Ciuc, S.D. Cotofana, Hierarchical Models for Intelligent Reconfigurable Simulation (March 2004), 15th IASTED International Conference on Modelling and Simulation (MS 2004), 1-3 March 2004, Marina del Rey, USA [Conference Paper]
  171. P. Celinski, S.F. Al-Sarawi, D. Abbott, S.D. Cotofana, S. Vassiliadis, Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach955_logical_effort_based_design_exploration_of_64bit_adders_usi.pdf (February 2004), IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 19-20 February 2004, Lafayette, USA [Conference Paper]
  172. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, GRAAL - A Development Framework for Embedded Graphics Accelerators953_graal__a_development_framework_for_embedded_graphics_accele.pdf (February 2004), Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France [Conference Paper]
  173. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, Compositional Memory Systems for Data Intensive Applications952_compositional_memory_systems_for_data_intensive_applications.pdf (February 2004), Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France [Conference Paper]
  174. T. Niculiu, C. Aktouf, S.D. Cotofana, Hierarchical Testability Assisted Intelligent Simulation (January 2004), International Journal of Modelling and Simulation, volume 24, issue 1 [Journal Paper]
  175. S. Wong, S. Vassiliadis, S.D. Cotofana, Future Directions of Programmable and Reconfigurable Embedded Processors998_future_directions_of_programmable_and_reconfigurable_embedde.pdf (January 2004), Chapter "Domain-Specific Processors: Systems, Architectures, Modeling and Simulation", Published by Marcel Dekker Inc. [Book Chapter]
  176. 2003

  177. T. Niculiu, S.D. Cotofana, Hierarchical Templates for Simulated Intelligence1052_hierarchical_templates_for_simulated_intelligence.pdf (December 2003), Simulation News Europe (SNE) , issue 38/39 [Journal Paper]
  178. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Evaluation Methodology for Single Electron Encoded Threshold Logic Gates1050_evaluation_methodology_for_single_electron_encoded_threshol.pdf (December 2003), International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC 2003), 1-3 December 2003, Darmstadt, Germany [Conference Paper]
  179. A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven, B. Mesman, Data Cache Optimization in Multimedia Applications1075_data_cache_optimization_in_multimedia_applications.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  180. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Building Blocks for Electron Counting Arithmetic1074_building_blocks_for_electron_counting_arithmetic.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  181. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single Electron Encoded SET Memory Elements1073_single_electron_encoded_set_memory_elements.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  182. M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, Inverse Quantization on FPGA-augmented TriMedia1072_inverse_quantization_on_fpgaaugmented_trimedia.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  183. P. Celinski, S.D. Cotofana, D. Abbott, Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates1071_logical_effort_delay_modeling_of_sense_amplifier_based_char.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  184. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, Design Tradeoffs for an Embedded OpenGL-Compliant Hardware Rasterizer1061_design_tradeoffs_for_an_embedded_openglcompliant_hardware.pdf (November 2003), 14th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003), 27-29 November 2003, Veldhoven, The Netherlands [Conference Paper]
  185. P.T. Stathis, S. Vassiliadis, S.D. Cotofana, D-SAB: A Sparse Matrix Benchmark Suite1006_dsab_a_sparse_matrix_benchmark_suite.pdf (September 2003), 7th International Conference on Parallel Computing Technologies (PaCT 2003), 15-19 September 2003, Novosibirsk, Russia [Conference Paper]
  186. D. Crisu, S.D. Cotofana, S. Vassiliadis, P. Liuha, High-Level Energy Estimation for ARM-Based SOCs1022_highlevel_energy_estimation_for_armbased_socs.pdf (July 2003), 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2003), 21-23 July 2003, Samos, Greece [Conference Paper]
  187. S. Vassiliadis, S. Wong, S.D. Cotofana, Microcode Processing: Positioning and Directions1020_microcode_processing_positioning_and_directions.pdf (July 2003), IEEE Micro, volume 23, issue 4 [Journal Paper]
  188. M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, Color Space Conversion for MPEG Decoding on FPGA-augmented TriMedia Processor1026_color_space_conversion_for_mpeg_decoding_on_fpgaaugmented.pdf (June 2003), 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands [Conference Paper]
  189. P. Celinski, S.D. Cotofana, D. Abbott, A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder1025_adelta_a_64bit_high_speed_compact_hybrid_dynamiccmos.pdf (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]
  190. T. Niculiu, S.D. Cotofana, Hierarchical Reconfigurable Simulated Intelligence Templates (June 2003), IASTED International Conference on Intelligent Systems and Control (ISC 2003), 25–27 June 2003, Salzburg, Austria [Conference Paper]
  191. M.D. Padure, S.D. Cotofana, S. Vassiliadis, CMOS Implementation of Generalized Threshold Functions (June 2003), 7th International Work-Conference on Artificial and Natural Neural Networks (IWANN 2003), 3-6 June 2003, Menorca, Spain [Conference Paper]
  192. S.D. Cotofana, C.R. Lageweg, S. Vassiliadis, On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge1027_on_computing_addition_related_arithmetic_operations_via_con.pdf (June 2003), 16th IEEE Symposium on Computer Arithmetic (ARITH-16 2003), 15-18 June 2003, Santiago de Compostela, Spain [Conference Paper]
  193. M.D. Padure, S.D. Cotofana, S. Vassiliadis, Design and Experimental Results of a CMOS Flip-Flop Featuring Embedded Threshold Logic (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]
  194. P. Celinski, S.D. Cotofana, D. Abbott, Area Efficient, High Speed Parallel Counter Circuits Using Charge Recycling Threshold Logic1033_area_efficient_high_speed_parallel_counter_circuits_using.pdf (May 2003), International Symposium on Circuits and Systems (ISCAS 2003), 25-28 May 2003, Bangkok, Thailand [Conference Paper]
  195. P. Celinski, S.D. Cotofana, J.F. Lopez, S.F. Al-Sarawi, D. Abbott, State-of-the-Art in CMOS Threshold-Logic VLSI Gate Implementations and Applications1031_stateoftheart_in_cmos_thresholdlogic_vlsi_gate_implemen.pdf (May 2003), SPIE International Symposium on Microtechnologies for the New Millennium, 19-21 May 2003, San Agustín, Gran Canaria, Spain, Invited Paper [Conference Paper]
  196. T. Niculiu, S.D. Cotofana, Concurrent Engineering for Intelligent Simulation (April 2003), European Concurrent Engineering Conference (ECEC 2003), 14-16 April 2003, Plymouth, UK [Conference Paper]
  197. P.T. Stathis, S. Vassiliadis, S.D. Cotofana, A Hierarchical Sparse Matrix Storage Format for Vector Processors1038_a_hierarchical_sparse_matrix_storage_format_for_vector_proc.pdf (April 2003), 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France [Conference Paper]
  198. 2002

  199. P. Celinski, S.D. Cotofana, D. Abbott, Threshold Logic Parallel Counters for 32-bit Multipliers1132_threshold_logic_parallel_counters_for_32bit_multipliers.pdf (December 2002), International Symposium on Smart Materials, Nano- and Micro-Smart Systems, 2-4 December 2002, Melbourne, Australia [Conference Paper]
  200. S. Wong, B. Stougie, S.D. Cotofana, Alternatives in FPGA-based SAD Implementations1129_alternatives_in_fpgabased_sad_implementations.pdf (December 2002), 1st IEEE International Conference on Field-Programmable Technology (FPT 2002), 16-18 December 2002, Hong Kong, China [Conference Paper]
  201. S. Wong, B. Stougie, S.D. Cotofana, An Investigation on FPGA Based SAD Hardware Implementations1154_an_investigation_on_fpga_based_sad_hardware_implementations.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  202. M.D. Padure, S.D. Cotofana, S. Vassiliadis, High-speed Hybrid Threshold-Boolean Logic1134_highspeed_hybrid_thresholdboolean_logic.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  203. M.D. Padure, S.D. Cotofana, S. Vassiliadis, A CMOS Flip-flop Featuring Embedded Threshold Logic Functions1133_a_cmos_flipflop_featuring_embedded_threshold_logic_functio.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  204. D. Crisu, S.D. Cotofana, S. Vassiliadis, A Hardware/Software Co-Simulation Environment For Graphics Accelerator Development in ARM-based SOCs1153_a_hardwaresoftware_cosimulation_environment_for_graphics.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  205. W. Zwart, J. Eilers, G.N. Gaydadjiev, S.D. Cotofana, DAMP - Delft Altera-based multimedia platform1141_damp__delft_alterabased_multimedia_platform.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  206. M. Sima, S. Vassiliadis, J.T.J. van Eijndhoven, S.D. Cotofana, YUV-to-RGB Color Space Conversion on FPGA-augmented TriMedia-32 Processor1140_yuvtorgb_color_space_conversion_on_fpgaaugmented_trimedi.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  207. S. Wong, G. Luo, S.D. Cotofana, Synthetic Benchmark Generator for the MOLEN Processor1139_synthetic_benchmark_generator_for_the_molen_processor.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  208. P.T. Stathis, S. Vassiliadis, S.D. Cotofana, Design considerations of a multiple inner product and accumulate vector functional unit1166_design_considerations_of_a_multiple_inner_product_and_accum.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  209. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A family of single electron static buffered Boolean logic1137_a_family_of_single_electron_static_buffered_boolean_logic.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  210. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, 7/3 and 7/2 Counters implemented in single electron technology1135_73_and_72_counters_implemented_in_single_electron_technol.pdf (November 2002), 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002), 27-29 November 2002, Veldhoven, The Netherlands [Conference Paper]
  211. T. Niculiu, C. Aktouf, S.D. Cotofana, High-level intelligence-oriented simulation1146_highlevel_intelligenceoriented_simulation.pdf (October 2002), International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania [Conference Paper]
  212. M.D. Padure, S.D. Cotofana, C. Dan, S. Vassiliadis, M. Bodea, Compact Delay Modeling of Latch-based Threshold Logic Gates1160_compact_delay_modeling_of_latchbased_threshold_logic_gates.pdf (October 2002), International Semiconductor Conference (CAS 2002), 8-12 October 2002, Sinaia, Romania, Best Paper Award [Conference Paper]
  213. S. Wong, S. Vassiliadis, S.D. Cotofana, A Sum of Absolute Differences Implementation in FPGA Hardware1091_a_sum_of_absolute_differences_implementation_in_fpga_hardwa.pdf (September 2002), 28th EUROMICRO Conference (EUROMICRO 2002), 4-6 September 2002, Dortmund, Germany [Conference Paper]
  214. M.D. Padure, S.D. Cotofana, S. Vassiliadis, C. Dan, M. Bodea, A low-power threshold logic family1090_a_lowpower_threshold_logic_family.pdf (September 2002), 9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia [Conference Paper]
  215. M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, K.A. Vissers, Field-Programmable Custom Computing Machines - A Taxonomy1089_fieldprogrammable_custom_computing_machines__a_taxonomy.pdf (September 2002), 12th International Conference on Field-Programmable Logic and Applications (FPL 2002), 2-4 September 2002, Montpellier, France [Conference Paper]
  216. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A full adder implementation using SET based linear threshold gates1088_a_full_adder_implementation_using_set_based_linear_threshol.pdf (September 2002), 9th IEEE International conference on electronics, circuits and systems (ICECS 2002), 15-18 September 2002, Dubrovnik, Croatia [Conference Paper]
  217. M.D. Padure, S.D. Cotofana, S. Vassiliadis, High-speed hybrid threshold-Boolean logic counters1100_highspeed_hybrid_thresholdboolean_logic_counters.pdf (August 2002), 45th Midwest Symposium on Circuits and Systems (MWSCAS 2002), 4-7 August 2002, Tulsa, USA [Conference Paper]
  218. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Static buffered SET based logic gates1099_static_buffered_set_based_logic_gates.pdf (August 2002), 2nd IEEE Conference on Nanotechnology (IEEE-NANO 2002), 26-28 August 2002, Washington DC, USA [Conference Paper]
  219. S. Wong, S.D. Cotofana, On Teaching Embedded Systems Design to Electrical Engineering Students1105_on_teaching_embedded_systems_design_to_electrical_engineeri.pdf (July 2002), 3rd International Conference on Information Communication Technologies in Education (ICICTE 2002), 17-19 July 2002, Samos, Greece [Conference Paper]
  220. S. Wong, S. Vassiliadis, S.D. Cotofana, Future Directions of (Programmable and Reconfigurable) Embedded Processors1104_future_directions_of_programmable_and_reconfigurable_embe.pdf (July 2002), 2nd International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), 22-25 July 2002, Samos, Greece [Conference Paper]
  221. M. Sima, E.J. Pol, J.T.J. van Eijndhoven, S.D. Cotofana, S. Vassiliadis, Entropy Decoding on TriMedia/CPU641106_entropy_decoding_on_trimediacpu64.pdf (July 2002), 2nd International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2002), 22-25 July 2002, Samos, Greece [Conference Paper]
  222. T. Niculiu, S.D. Cotofana, Hierarchical Intellignet Mixed Simulation1113_hierarchical_intellignet_mixed_simulation.pdf (June 2002), 16th European Simulation Multiconference: Modelling and Simulation (ESM 2002), 3-5 June 2002, Darmstadt, Germany [Conference Paper]
  223. I. Lemberski, M. Koegst, S.D. Cotofana, B.H.H. Juurlink, FSM Non-minimal state encoding for low power1115_fsm_nonminimal_state_encoding_for_low_power.pdf (May 2002), 23rd International Conference on Microelectronics, 12-15 May 2002, Nis, Yugoslavia [Conference Paper]
  224. S.D. Cotofana, P.T. Stathis, S. Vassiliadis, Direct and transposed sparse matrix-vector multiplication1123_direct_and_transposed_sparse_matrixvector_multiplication.pdf (April 2002), 4th International Conference on Massively Parallel Computing Systems (MPCS 2002), 10-12 April 2002, Ischia, Italy [Conference Paper]
  225. M. Sima, S.D. Cotofana, S. Vassiliadis, MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU641118_mpegcompliant_entropy_decoding_on_fpgaaugmented_trimedia.pdf (April 2002), 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002 , Napa, USA [Conference Paper]
  226. D. Crisu, S.D. Cotofana, S. Vassiliadis, A proposal of a tile-based open GL compliant rasterization engine (January 2002), CE technical report [Technical Report]
  227. 2001

  228. D. Crisu, S.D. Cotofana, S. Vassiliadis, An energy-aware architectural exploration tool for ARM-based SOCs1222_an_energyaware_architectural_exploration_tool_for_armbase.pdf (November 2001), 12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  229. S. Wong, S. Vassiliadis, S.D. Cotofana, SAD Implementation in FPGA Hardware1221_sad_implementation_in_fpga_hardware.pdf (November 2001), 12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  230. P.T. Stathis, S.D. Cotofana, S. Vassiliadis, Sparse Matrix Vector Multiplication Evaluation Using the BBCS scheme1220_sparse_matrix_vector_multiplication_evaluation_using_the_bb.pdf (November 2001), 8th Panhellenic Conference on Informatics , 8-10 November 2001, Nicosia, Cyprus [Conference Paper]
  231. P.T. Stathis, S. Vassiliadis, S.D. Cotofana, Transposition Mechanism for sparse matrices on vector processors1219_transposition_mechanism_for_sparse_matrices_on_vector_proce.pdf (November 2001), 12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  232. M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, Variable-Length Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit1218_variablelength_decoder_implemented_on_a_trimediacpu64_rec.pdf (November 2001), 12th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2001), 29-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  233. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Single electron encoded logic circuits1213_single_electron_encoded_logic_circuits.pdf (November 2001), 4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  234. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A turnstile based single electron memory element1212_a_turnstile_based_single_electron_memory_element.pdf (November 2001), 4th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (SAFE 2001), 28-30 November 2001, Veldhoven, The Netherlands [Conference Paper]
  235. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Achieving fanout capabilities in single electron encoded logic networks1227_achieving_fanout_capabilities_in_single_electron_encoded_lo.pdf (October 2001), 6th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2001), 22-25 October 2001, Shanghai, China [Conference Paper]
  236. M.D. Padure, S.D. Cotofana, C. Dan, M. Bodea, S. Vassiliadis, A new latch-based threshold logic family1231_a_new_latchbased_threshold_logic_family.pdf (October 2001), International Semiconductor Conference (CAS 2001), 9-13 October 2001, Sinaia, Romania [Conference Paper]
  237. M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis, An 8-point IDCT Computing Resource Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit1230_an_8point_idct_computing_resource_implemented_on_a_trimedi.pdf (October 2001), 2nd Workshop on Embedded Systems (PROGRESS 2001), 18 October 2001, Veldhoven, The Netherlands [Conference Paper]
  238. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, Digital to analog conversion performed in single electron technology1228_digital_to_analog_conversion_performed_in_single_electron_t.pdf (October 2001), 1st IEEE Conference on Nanotechnology (IEEE-NANO 2001), 28-30 October 2001, Maui, USA [Conference Paper]
  239. M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, K.A. Vissers, MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor1175_mpeg_macroblock_parsing_and_pel_reconstruction_on_an_fpgaa.pdf (September 2001), 19th International Conference on Computer Design (ICCD 2001), 23-26 September 2001, Austin, USA [Conference Paper]
  240. T. Niculiu, C. Aktouf, S.D. Cotofana, MultiHierarchical Intelligent Simulation (August 2001), Polytechnical University of Bucharest Scientific Bulletin, Series C: Electrical Engineering, volume 63, issue 3-4 [Journal Paper]
  241. S. Vassiliadis, S. Wong, S.D. Cotofana, The MOLEN pu-coded Processor1177_the_molen_pucoded_processor.pdf (August 2001), 11th International Conference on Field-Programmable Logic and Applications (FPL 2001), 27-29 August 2001, Belfast, UK [Conference Paper]
  242. M. Sima, S.D. Cotofana, S. Vassiliadis, J.T.J. van Eijndhoven, K.A. Vissers, A Reconfigurable Functional Unit for TriMedia/CPU64: A Case Study1187_a_reconfigurable_functional_unit_for_trimediacpu64_a_case.pdf (July 2001), 1st International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2001), 16–18 July 2001, Samos, Greece [Conference Paper]
  243. S. Wong, S. Vassiliadis, S.D. Cotofana, Microcoded Reconfigurable Embedded Processors: Current Developments1185_microcoded_reconfigurable_embedded_processors_current_deve.pdf (July 2001), 1st International Samos Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2001), 16–18 July 2001, Samos, Greece [Conference Paper]
  244. S. Vassiliadis, S. Wong, S.D. Cotofana, Network Processors: Issues and Prospectives1193_network_processors_issues_and_prospectives.pdf (June 2001), International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2001), 25-28 June 2001, Las Vegas, USA [Conference Paper]
  245. T. Niculiu, S.D. Cotofana, Hierarchical intelligent simulation1191_hierarchical_intelligent_simulation.pdf (June 2001), 15th European Simulation Multiconference (ESM 2001), 6-9 June 2001, Prague, Czech Republic [Conference Paper]
  246. E. Moscu Panainte, I. Athanasiu, S.D. Cotofana, An Optimization Framework for Retargetable Compilers (May 2001), 13th International Conference on Control Systems and Computer Sciences (CSCS 2001), May 2001, Bucharest, Romania [Conference Paper]
  247. S.D. Cotofana, S. Wong, S. Vassiliadis, Embedded Processors: Characteristics and Trends1198_embedded_processors_characteristics_and_trends.pdf (May 2001), 7th Annual Conference of the Advanced School for Computing and Imaging (ASCI 2001), 30 May - 1 June 2001, Heijen, The Netherlands [Conference Paper]
  248. T. Niculiu, S.D. Cotofana, Multi-hierarchical learning-based co-simulation1196_multihierarchical_learningbased_cosimulation.pdf (May 2001), IASTED International Conference on Modelling and Simulation (MS 2001), 16-18 May 2001, Pittsburg, USA [Conference Paper]
  249. M. Sima, S.D. Cotofana, J.T.J. van Eijndhoven, S. Vassiliadis, K.A. Vissers, An 8x8 IDCT Implementation on an FPGA-augmented TriMedia1204_an_8x8_idct_implementation_on_an_fpgaaugmented_trimedia.pdf (April 2001), 9th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2001), 29 April - 2 May 2001, Rohnert Park, USA [Conference Paper]
  250. C.R. Lageweg, S.D. Cotofana, S. Vassiliadis, A linear threshold gate implementation in single electron technology1202_a_linear_threshold_gate_implementation_in_single_electron_t.pdf (April 2001), IEEE Computer Society Workshop on VLSI (WVLSI 2001), 19-20 April 2001, Orlando, USA [Conference Paper]
  251. S. Wong, S.D. Cotofana, S. Vassiliadis, Coarse Reconfigurable Multimedia Unit Extension1208_coarse_reconfigurable_multimedia_unit_extension.pdf (February 2001), 9th Euromicro Workshop on Parallel and Distributed Processing (PDP 2001), 7-9 February 2001, Mantova, Italy [Conference Paper]
  252. S. Vassiliadis, S. Wong, S.D. Cotofana, The MOLEN pu-coded Processor1240_the_molen_pucoded_processor.pdf (January 2001), CE technical report [Technical Report]
  253. 2000

  254. M. Sima, S. Vassiliadis, S.D. Cotofana, J.T.J. van Eijndhoven, K.A. Vissers, 1st Workshop on Embedded Systems1282_1st_workshop_on_embedded_systems.pdf (October 2000), 1st Workshop on Embedded Systems (PROGRESS 2000), 13 October 2000, Utrecht, The Netherlands [Conference Paper]
  255. T. Niculiu, S.D. Cotofana, A. Manolescu, Hierarchical approach for hardware/software systems1280_hierarchical_approach_for_hardwaresoftware_systems.pdf (October 2000), 23rd International Semicondutor Conference (CAS 2000), 10-14 October 2000, Sinaia, Romania [Conference Paper]
  256. S.D. Cotofana, B.H.H. Juurlink, S. Vassiliadis, Counter Based Superscalar Instruction Issuing1245_counter_based_superscalar_instruction_issuing.pdf (September 2000), 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future (EUROMICRO 2000), 5-7 September 2000, Maastricht, The Netherlands [Conference Paper]
  257. S. Vassiliadis, S.D. Cotofana, P.T. Stathis, BBCS based sparse matrix-vector multiplication: initial evaluation1252_bbcs_based_sparse_matrixvector_multiplication_initial_eva.pdf (August 2000), 16th IMACS World Congress on Scientific Computation, Applied Mathematics and Simulation (IMACS 2000), 21-25 August 2000, Lausanne, Switzerland [Conference Paper]
  258. M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Hashed Addressed Caches for Embedded Pointer Based Codes1251_hashed_addressed_caches_for_embedded_pointer_based_codes.pdf (August 2000), 6th International Euro-Par Conference on Parallel Processing (Euro-Par 2000), 29 August - 1 September 2000, Munich, Germany [Conference Paper]
  259. S. Wong, S.D. Cotofana, S. Vassiliadis, Multimedia Enhanced General-Purpose Processors1254_multimedia_enhanced_generalpurpose_processors.pdf (July 2000), IEEE International Conference on Multimedia and Expo (ICME 2000), 30 July - 2 August 2000, New York, USA [Conference Paper]
  260. S. Vassiliadis, S.D. Cotofana, P.T. Stathis, Block Based Compression Storage Expected Performance1262_block_based_compression_storage_expected_performance.pdf (June 2000), 14th International Conference on High Performance Computing Systems and Applications (HPCS 2000), 14-17 June 2000, Victoria, Canada [Conference Paper]
  261. T. Niculiu, C. Aktouf, S.D. Cotofana, Hierarchical interfaces for hardware/software systems1263_hierarchical_interfaces_for_hardwaresoftware_systems.pdf (May 2000), 14th European Simulation Multiconference - Simulation and Modelling: Enablers for a Better Quality of Life (ESM 2000), 23-26 May 2000, Ghent, Belgium [Conference Paper]
  262. S.D. Cotofana, S. Vassiliadis, Signed digit addition and related operations with threshold logic1269_signed_digit_addition_and_related_operations_with_threshold.pdf (March 2000), IEEE Transactions on Computers (TC) , volume 49, issue 3 [Journal Paper]
  263. S. Wong, S.D. Cotofana, S. Vassiliadis, General-Purpose Processor Huffman Encoding Extension1268_generalpurpose_processor_huffman_encoding_extension.pdf (March 2000), International Conference on Information Technology: Coding and Computing (ITCC 2000), 27-29 March 2000, Las Vegas, USA [Conference Paper]
  264. M. Stanca, H. Corporaal, S.D. Cotofana, S. Vassiliadis, Array Based Structure Loop Transformations for Cache Miss Reduction1274_array_based_structure_loop_transformations_for_cache_miss_r.pdf (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]
  265. A. Berlea, S.D. Cotofana, I. Athanasiu, C.J. Glossner, S. Vassiliadis, Garbage collection for the Delft Java Processor1270_garbage_collection_for_the_delft_java_processor.pdf (February 2000), 18th IASTED International Conference on Applied Informatics (AI 2000), 14-17 February 2000, Innsbruck, Austria [Conference Paper]
Sorin Cotofana