# Publications

## Technology / Device Modelling

- S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny,
**VTEAM – A General Model for Voltage Controlled Memristor**, IEEE Transactions on Circuits and Systems II: Express Briefs (in press). - S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**The Desired Memristor for Circuit Designers**, IEEE Circuits and Systems Magazine, Vol. 13, No. 2, pp. 17-22, May 2013. - S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**TEAM - ThrEshold Adaptive Memristor Model**, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 1, pp. 211-221, January 2013. - S. Kvatinsky, K. Talisveyberg, D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Models of Memristors for SPICE Simulations**, Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012.

## Reliability / Sneakpath

- L. Xie, H.A. Du Nguyen, J. Yu, M. Taouil, and S. Hamdioui,
**On the Robustness of Memristor Based Logic Gates**, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, Germany, April 2017. - Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
**On the Channel Induced by Sneak-Path Errors in Memristor Arrays**, Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014. - Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
**Sneak-Path Constraints in Memristor Crossbar Arrays**, Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013. - Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
**Sneak-Path Constraints in Memristor Crossbar Arrays**, Proceeding of the Annual Non-Volatile Memories Workshop, March 2013.

## Logic/Circuit

- L. Xie, H.A. Du Nguyen, J. Yu, A. Kaichouhi, M. Taouil, and S. Hamdioui,
**Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing**, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany, July 2017. - L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels, and M Alfailakawi,
**Non-Volatile Look-up Table Based FPGA Implementations**, 11th IEEE International Design & Test Symposium (IDT 2016), Hammamet, Tunisia, December 2016. - L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, K.L.M. Bertels,
**Boolean Logic Gate Exploration for Memristor Crossbar**, 11th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2016), Istanbul, Turkey, April 2016. - L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, and K.L.M. Bertels,
**Fast Boolean Logic Mapped on Memristor Crossbar**, 33rd IEEE International Conference on Computer Design (ICCD 2015), New York, USA, October 2015. - L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, and K.L.M. Bertels,
**Interconnect Networks for Memristor Crossbar**, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), Boston, USA, July 2015. - H.A. Du Nguyen, L. Xie, R. Nane, M. Taouil, S. Hamdioui, K.L.M. Bertels,
**Computation-In-Memory Based Parallel Adder**, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), Boston, USA, July 2015. - L. Yavits, S. Kvatinsky, A. Morad, and R. Ginosar,
**Resistive Associative Processor**, IEEE Computer Architecture Letters (in press). - D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky,
**Memristor-based Multilayer Neural Networks with Online Gradient Descent Training**, IEEE Transactions on Neural Networks and Learning Systems (in press). - E. Linn, "Memristive Devices - The key enabler for CIM architecture implementation," DATE Conference, March 2015.
- M. Klimo, J. Smiesko, E. Linn, and O. Šuch,
**Modeling MIN and MAX gates using memristive devices**, Workshop on Memristor Technology, Design, Automation and Computing (MemTDAC), January 2015. - L. Nielen, A. Siemon, S. Tappertzhofen, R. Waser, S. Menzel, and E. Linn,
**Memristive Associative Capacitive Networks - A Novel Approach for Fully Parallel Pattern Recognition**, Workshop on Memristor Technology, Design, Automation and Computing (MemTDAC), January 2015. - Y. Levy, J. Bruck, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaacobi, and S. Kvatinsky,
**Logic Operation in Memory Using a Memristive Akers Array**, Microelectronics Journal, Vol. 45, No. 11, pp. 1429-1437, November 2014. - S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**MAGIC – Memristor Aided LoGIC**, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 895-899, November 2014. - S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies**, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 22, No. 10, pp. 2054-2066, October 2014. - S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Memory Intensive Computing**, Proceeding of the Annual Non-Volatile Memories Workshop, March 2014. - S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**MRL – Memristor Ratioed Logic**, Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012. - S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Memristor-based IMPLY Logic Design Flow**, Proceedings of the IEEE International Conference on Computer Design, pp.142-147, October 2011.

## Memory

- R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny,
**Multistate Register Based on Resistive RAM**, IEEE Transactions on Very Large Scale Integration (VLSI), (in press). - S. Menzel, E. Linn, and R. Waser, Emerging Nanoelectronic Devices, Chapter:
**Redox-based Resistive Memory**, Wiley, 2015, pp. 137-161. - Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, J. Kang, and H.-S. P. Wong,
**Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array**, Proceedings of the 2015 International Memory Workshop, May 2015. - M.Komalan, I.Gomez, C.Tenllado, F.Tirado, F.Catthoor,
**System level exploration of a STT-MRAM based Level 1 Data-Cache**, Proc. 18th ACM/IEEE Design and Test in Europe Conf.(DATE), Grenoble, France, pp., March 2015. - M.Komalan, I.Gomez, C.Tenllado, P.Raghavan, M.Hartmann, F.Catthoor,
**Design exploration of a NVM based hybrid instruction memory organization for embedded platforms**, Design Automation for Embedded Systems (DAES), Springer Science Publ., Boston, Vol.17, No.3-4, pp.459-483, Oct 2014 - S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Memristive Multistate Pipeline Register**, Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014. - S. Hamdioui, H Aziza, G. Ch Sirakoulis,
**Memristor Based Memories: Technology, Design and Test**, IEEE 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2014), 6-8 May 2014, Santorini, Greece - M.Hartmann, H.Kukner, P.Agrawal, P.Raghavan, L.Van Der Perre, W.Dehaene,
**Modeling and mitigation of time-zero variability in sub-16 nm finfet-based STT-MRAM memories**, Proc. IEEE Great Lakes Symp. on VLSI, Houston, TX, pp.243-244, May 2014. - M.Komalan, I.Gomez, C.Tenllado, P.Raghavan, M.Hartmann, F.Catthoor
**, Feasibility Exploration of NVM based I-Cache through MSHR Enhancements**, Proc. 17th ACM/IEEE Design and Test in Europe Conf.(DATE), Dresden, Germany, pp.1-6, March 2014. - M.Hartmann, P.Raghavan, P.Agrawal, L.Van Der Perre, W.Dehaene,
**Memristor-based (ReRAM) Data Memory Architecture in ASIP Design**, Proc. Euromicro Symp. on Digital System Design (DSD), Santander, Spain, pp.-, Sep. 2013. - M.Komalan, A.Artes, C.Tenllado, I.Gomez, M.Hartmann, F.Catthoor,
**System level exploration of resistive-RAM (ReRAM) based hybrid instruction memory organization**, MeAOW wsh, Tampere, Finland, Oct. 2012.

## Architecture

- S. Hamdioui, S Kvatinsky, G Cauwenberghs, L. Xie, N Wald, S Joshi, H Elsayed, H. Corporaal, and K.L.M. Bertels,
**Memristor For Computing: Myth or Reality?, Design, Automation and Test in Europe**, Lausanne, Switzerland, March 2017. - H.A. Du Nguyen, L. Xie, M. Taouil, R. Nane, S. Hamdioui, and K.L.M. Bertels,
**On the Implementation of Computation-in-Memory Parallel Adder**, IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), May 2017. - H.A. Du Nguyen, L. Xie, J. Yu, M. Taouil, and S. Hamdioui,
**Interconnect Networks for Resistive Computing Architectures,**12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS 2017), Palma de Mallorca, Spain, April 2017. - M.A.B. Haron, J. Yu, R. Nane, M. Taouil, S. Hamdioui, and K.L.M. Bertels,
**Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture**, International Conference on High Performance Computing & Simulation (HPCS 2016), Innsbruck, Austria, July 2016. - S. Hamdioui, M. Taouil, H.A. Du Nguyen, M.A.B. Haron, L. Xie, and K.L.M. Bertels,
**Memristor: The Enabler of Computation-in-Memory Architecture for Big-Data, International Conference on Memristive Systems,**MEMRISYS, Paphos, Cyprus, November 2015. - S. Hamdioui, H.A. Du Nguyen, M. Taouil, K.L.M. Bertels,
**Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications**, 18th Design, Automation & Test in Europe conference (DATE 2015), 9-13 March 2015, Grenoble, France - S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser,
**Memristor-Based Multithreading**, IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014.

## Design Automation

- L. Xie, H.A. Du Nguyen, M. Taouil, S. Hamdioui, and K.L.M. Bertels,
**A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar**, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), April 2017. - J. Yu, R. Nane, I. Ashraf, M. Taouil, S. Hamdioui, H. Corporaal, and K.L.M. Bertels,
**Skeleton-based Synthesis Flow for Computation-In-Memory Architectures**, IEEE Transactions on Emerging Topics in Computing (TETC) (in press). - J. Yu, T. Hogervorst, and R. Nane, A Domain-Specific Language and Compiler for Computation-in-Memory, 27th ACM Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Canada, May 2017.
- J. Yu, R. Nane, M.A.B. Haron, S. Hamdioui, H. Corporaal, and K.L.M. Bertels,
**Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures**, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), Beijing, China, July 2016. - H.A. Du Nguyen, L. Xie, M. Taouil, S. Hamdioui, and K.L.M. Bertels,
**Synthesizing HDL to memristor technology: A generic framework**, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2016), Beijing, China, July 2016.

## Test

- S. Hamdioui, M. Taouil, N.Z.B. Haron,
**Testing Open Defects in Memristor-Based Memories**, IEEE Transactions on Computers (TC) , volume 64, pp 247-459, 2015

## News

This website is still under construction.