Current research on Quantum Computing

I am a principal investigator in the Qutech research center and responsible for the quantum architecture and system design aspects. This involves the following topics:

  1. The overall heterogeneous micro-architecture of a quantum compuer
  2. The architecture of the qubit plane
  3. Classical (and thus limited) simulation of a quantum computer
  4. Compiling for quantum


 Past research

My past research was driven by the need to make heterogeneous multicore processors more easily programmable and to fully exploit the available hardware in a way which is as transparent as possible for the developer. However, the times where developers do not need to know any low level detail of the processor architecture are over.  Especially when reconfigurable computing components such as FPGA blades are available, this becomes especially challenging as it assumes hardware design expertise to be able to use them.  The inclusion of such components is increasingly popular, both for embedded systems as well as for supercomputing.  Examples of current day platforms are : the Zynq from Xilinx or IBM's Power 8 with CAPI interfaces to plug in FPGA blades.  Another nice example was the Convey supercomputer which was bought by Micro.

The main challenge is to exploit in an efficient way the different computing elements and how the hardware should evolve with the specific needs of the application which is being executed.

Relevant publications are : 

  1. On hardware-software co-design
    1. K.L.M. Bertels, V.M. Sima, Y.D. Yankova, G.K. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada,D. Sciuto, A. Michelotti, hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms (October 2010), IEEE Micro, volume 30, issue 5 , Special Issue on European Multicore Processing Projects
  2. On placement of tasks on the reconfigurable area
    1. Y. Lu, T. Marconi, K.L.M. Bertels, G.N. Gaydadjiev, Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems (March 2009), 5th International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2009), 16-18 March 2009, Karlsruhe, Germany
    2. T. Marconi, Y. Lu, K.L.M. Bertels, G.N. Gaydadjiev, Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems (March 2008), Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany
    3. Y. Lu, T. Marconi, K.L.M. Bertels, G.N. Gaydadjiev, A Communication Aware Online Task Scheduling Algorithm for FPGA-based Partially Reconfigurable Systems (May 2010), 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), 2-4 May 2010, Charlotte, USA
    4. Y. Lu, K.L.M. Bertels, G.N. Gaydadjiev, Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems (December 2010), International Conference on Field-Programmable Technology (FPT 2010), 8-10 December 2010, Beijing, China
  3. On compiler related issues for heterogeneous multicore
    1. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiling for the Molen Programming Paradigm 2003), 13th International Conference on Field Programmable Logic and Applications (FPL 2003), 1-3 September 2003, Lisbon, Portugal
    2. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany 
    3. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany
    4. R. Nane, V.M. Sima, C. Pilato, J. Choi, B Fort, A Canis, Y.T. Chen, H Hsiao, S Brown, F. Ferrandi, J Anderson,K.L.M. Bertels, A Survey and Evaluation of FPGA High-Level Synthesis Tools (December 2015), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
    5. R. Nane, V.M. Sima, B Olivier, R.J. Meeuws, Y.D. Yankova, K.L.M. Bertels, DWARV 2.0: A CoSy-based C-to-VHDL Hardware Compiler (August 2012), 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), 29-31 August 2012, Oslo, Norway
  4. On instruction set extensions
    1. C. Galuzzi, K.L.M. Bertels, S. Vassiliadis, A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions (July 2008), International Journal of Electronics (IJE)
    2. C. Galuzzi, K.L.M. Bertels, S. Vassiliadis, A Linear Complexity Algorithm for the Generation of Multiple Inputs Single Output Instructions of Variable Size (July 2007), 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2007), 16-19 July 2007, Samos, Greece
  5. On data-driven profiling of applications
    1. S.A. Ostadzadeh, R.J. Meeuws, C. Galuzzi, K.L.M. Bertels, QUAD - A Memory Access Pattern Analyser 2010), 6th International Symposium on Applied Reconfigurable Computing (ARC 2010), 17-19 March 2010, Bangkok, Thailand
    2. I. Ashraf, K.L.M. Bertels, N. Khammassi, J.C. Le Lann, Communication-aware Parallelization Strategies for High Performance Applications (July 2015), IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 08-10 July 2015, Montpellier, France
    3. I. Ashraf, V.M. Sima, K.L.M. Bertels, Intra-Application Data-Communication Characterization (July 2015), 1st International Workshop on Communication Architectures at Extreme Scale (ExaComm 2015), 16 July 2015, Frankfurt, Germany
    4. I. Ashraf, S.A. Ostadzadeh, R.J. Meeuws, K.L.M. Bertels, Communication-aware HW/SW Co-design for Heterogeneous Multicore Platforms (July 2012), 10th International Workshop on Dynamic Analysis (WODA 2012), 15 July 2012, Minneapolis, USA
  6. On runtime for reconfigurable processors
    1. V.M. Sima, K.L.M. Bertels, Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform (May 2009), 16th Reconfigurable Architectures Workshop (RAW 2009), 25-26 May 2009, Rome, Italy
    2. G. Mariani, V.M. Sima, G. Palermo, V. Zaccaria, C. Silvano, K.L.M. Bertels, Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures (March 2012),Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), 12-16 March 2012, Dresden, Germany
  7. On bio-informatics acceleration
    1. L. Hasan, Z. Al-Ars, Z. Nawaz, K.L.M. Bertels, Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia
    2. Z. Nawaz, M. Nadeem, J. van Someren, K.L.M. Bertels, A parallel FPGA design of the Smith-Waterman traceback (December 2010), International Conference on Field-Programmable Technology (FPT 2010), 8-10 December 2010, Beijing, China
    3. Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Smith-Waterman Using Recursive Variable Expansion (September 2008), 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2008), 3-5 September 2008, Parma, Italy
    4. E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany 



Koen Bertels