Projects

I was involved in the following projects : 

  1. Morpheus : This FP6 project created a silicon prototype of the Molen polymorphic processor where an ARM was combined with 3 different reconfigurable fabrics on one die.  Besides the processor architecture, we were involved in the programming tool chain.
  2. Hartes aimed to lay the foundation for a new holistic (end-to-end) approach for complex real-time embedded system design, with the latest algorithm exploration tools and reconfigurable hardware technologies. From the application point of view, the complexity of future multimedia devices is becoming too big to design monolithic processing platforms. This is where the hArtes approach with reconfigurable heterogeneous systems becomes vital. The proposed approach addressed, for the first time, optimal and rapid design of embedded systems from high-level descriptions, targeting a combination of embedded processors, digital signal processing and reconfigurable hardware. We developed modular and scalable hardware platforms that can be reused and re-targeted by the tool chain to produce optimized real-time embedded products. The results were evaluated using advanced audio and video systems that support next-generation communication and entertainment facilities, such as immersive audio and mobile video processing.
    The outcomes of the project were described in the following book published by Springer Verlag : Hardware/Software Co-Design for Heterogeneous Multicore Processing.
    A spin off company, BlueBee b.v., was created to further mature and market the technology developed in hArtes. 
  3. SoftSoc : SoftSoC was a CATRENE project that aimed at solving the main SoC productivity bottleneck by providing Hardware Dependant Software (HDS) solutions to enable SoC designers to aggregate multiple HW IP with their associated HDS into efficient design. Delft worked with LIACS and Compaan Design on a tool flow that incorporated the DWARV hardware compiler and the Compaan design flow. The CE lab was the scientific and technical coordinator of the project as well as work package leader.
  4. SMECY envisionend that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments which, due to improved performance, energy and cost properties, will extensively penetrate the embedded system industry in a few years. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, IP providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The CE lab is involved in reliable computing, workload characterisation and virtualisation of different processor architectures.
  5. The iFEST project  (industrial Framework for Embedded Systems Tools) aims at specifying and developing an tool integration framework for HW/SW co-design of heterogeneous and multi-core embedded systems. The integration framework will permit tools to be readily replaced within the tool chain; thus dealing with issues such as tool obsolescence and tool lock-in. IFEST industrial case studies will validate the integration framework and tool chains for control and streaming applications. The CE lab is work package leader and responsible for the HW/SW co-design tools integration.
  6. The REFLECT project stands for Rendering FPGAs to Multi-Core Embedded Computing.  The REFLECT's approach intends to solve some of the problems when mapping efficiently computations to FPGA-based systems. In particular, the use of aspects and strategies will allow developers to try different design patterns and to achieve solutions design-guided by non-functional requirements. To the best of our knowledge, the REFLECT design flow is the first approach considering a systematic control of all the compilation stages and the first one to consider the relationship between non-functional requirements to different design patterns and optimizations, both specified in a domain-specific language, named LARA.The CE lab is work package leader and responsible for the DWARV hardware compiler which generates VHDL from the C-code which was augmented by aspects.
  7. EMC2‘Embedded Multi-Core systems for Mixed Criticality applications in dynamic and changeable real-time environments’ is an ARTEMIS Joint Undertaking project in the Innovation Pilot Programme ‘Computing platforms for embedded systems’ (AIPP5). Embedded systems are the key innovation driver to improve almost all mechatronic products with cheaper and even new functionalities. They support today’s information society as inter-system communication enabler. A major industrial challenge arises from the need to face cost efficient integration of different applications with different levels of safety and security on a single computing platform in an open context. EMC² finds solutions for dynamic adaptability in open systems, provides handling of mixed criticality applications under real-time conditions, scalability and utmost flexibility, full scale deployment and management of integrated tool chains, through the entire lifecycle. EMC² is a project of 99 partners of embedded industry and research from 19 European countries with an effort of about 800 person years and a total budget of about 100 million Euro.

 

 

 

 

Koen Bertels