Talks from Computer Engineering group, Tallinn University of Technology


Siavoosh Azad & Behrad Niazmand & Artjom Rjabov, Tallinn University of Technology (TUT), Estonia -- 07-07-2016


Talk 1: Fault tolerant mapping scheduling for NoC based systems

This presentation concentrates on a framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems. Where the system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework focuses on task clustering, mapping and scheduling of different applications, using different heuristics, on a NoC-based architecture which can have different topologies, fault monitoring mechanisms and different fault models.

 Talk 2: Addressing dependability of NoC-based Systems through concurrent online checkers and fault-tolerant routing

The extreme scaling of nano meter technologies and integration of more and more cores on the same chip, can make the circuitry more susceptible to different sources of faults. Even if faults are tried to be captured through methods such as manufacturing testing,  some faults can manifest themselves during the run time of the system. We intend to capture run-time faults by integrating micro modules, called a checkers, in a concurrent and online manner. To this end, we introduce an automated framework, which using two heuristic-based approaches, i.e. Greedy and Branch and Bound, it provides an optimized set of checkers meeting a target fault coverage and area constraint. Moreover, for the case of reconfigurable and fault-tolerant routing in NoCs, we have introduced a flexible, scalable and logic-based distributed mechanism (LBDR3D) which addresses partially connected 3D NoCs, which does not rely on the location of faulty links and does not need expensive routing tables at each node in the network. As long as the network has connectivity, LBDR3D is able to find a path, by setting its configuration bits.

Talk 3: Parallel Processing in Hardware Accelerators for Computationally Intensive Problems

We study computationally intensive problems are for applications in the following areas: combinatorial search (e.g. Boolean satisfiability and set/matrix covering); data processing (e.g. sort, search and frequent item computations). Many methods, that are used to solve such problems, possess the following common features: 1) the need for parallel processing of data streams (with such examples as sorting networks, Hamming weigh/distance counters applied to long-size vectors, operations over rows/columns of large matrices, etc.); 2) high repetition of operations (i.e. although the number of invoked operations is limited, each operation is very frequent and has to be applied to a huge volume of data); 3) the use of pipelines; 4) the need for concurrency and, thus, highly parallel algorithms have to be executed in hardware with the support for advanced control (such as that is used in hierarchical finite state machines). Our work focuses on the listed above features and concentrates on such hardware architectures that are the most appropriate. This presentation is focused mostly on hardware acceleration for data sorting.


Siavoosh Azad got  his M.Sc. in System on Chip in 2012 and Is currently working as an early stage researcher at Tallinn University of Technology his areas of interest are Dependability and fault tolerance of NoC based architectures.

Behrad Niazmand has acquired his Master's degree in Computer Engineering (Computer Architecture) from Science and Research Branch, Azad University in Tehran, Iran in 2012. Since, September 2014, he is studying as an early stage researcher (PhD student) in Information and communications technology at department of Computer Engineering at Tallinn University of Technology (TUT). His research interests are fault-tolerant routing mechanisms in NoCs, reliability and online fault detection mechanisms for NoCs, Reconfigurable architectures for routing in NoCs. He has had publications in conferences and he is also a student member of IEEE.

Artjom Rjabov received the M.Sc. degree in Computer Engineering from Tallinn University of Technology, Tallinn, Estonia, in 2013. He is currently an early stage researcher and Ph.D. candidate at the Department of Computer Engineering, Tallinn University of Technology, Estonia. He has authored and co-authored one book and 11 papers. His research interests include digital design, reconfigurable computing and application-specific architectures.




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