On-chip Interconnects: The Traffic Jam on the Road to Performance Scaling


James Clarke, Components Research, Intel Corporation, US -- 08-01-2015


Transistors continue to scale in both density and performance via novel architectures and novel materials.  However, the extension of these devices to useful circuits requires world class interconnect systems.  The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink.  At some point, the overall circuit density will be defined by the interconnects and not the device.  Stated more bluntly, the impact of novel transistors on end products may not be realized.

This talk will focus on the challenges of interconnect scaling, which are comprised of 1) density scaling, 2) resistance scaling, 3) capacitance scaling, and 4) reliability.    The industry has enjoyed a rather straightforward implementation of dual damascene metallization using conventional copper schemes for the past decade.  However, as research begins into dimensions below 10nm, these conventional methods run out of steam.  Resistance is increasing faster than the scale factor of the technology and causes a bottleneck in both local and global information transfer on a chip. 

Conductance is no longer determined by the bulk resistance of the copper wire.  Instead, electron scattering at wire sidewalls and at metal grains dominate resistivity.  Engineering below the nanometer length scale is required. There is substantial research into novel materials like carbon nanotubes and graphene that could eliminate scattering mechanisms, but presents additional challenges to implementation.  At the same time, capacitance scaling continues to be important and the insulators surrounding the copper wires require new materials development.

New paradigms for compute that could further mitigate interconnect bottlenecks will also be discussed.


Jim Clarke is the manager of metals and dielectric research within Intel’s Components Research Organization. His group's primary focus is on interconnect scaling beyond the 7nm technology node and evaluating new materials and paradigms for interconnect performance.  He has been at Intel since 2001.  Jim has received an Intel Achievement Award for interconnect development.  He has co-authored more than 50 papers and has several patents.  Prior to Intel, Jim completed his B.S. in honors chemistry at Indiana University and his Ph.D. in physical chemistry at Harvard University.  He also completed a post-doctoral fellowship in physical organic chemistry at Eidgenössische Technische Hochschule, Zürich.

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