Run time adaptive processing units using coarse and fine grain reconfigurable fabric


Ricardo Santos Ferreira, Department of Informatics DPI, Unversidade Federal de Vicosa, Brazil -- 16-09-2013


 In order to match application software with the underlying hardware, we propose to use run time information to better design processors and accelerators, while still allowing for binary compatibility to obtain gains at the system level. Two main techniques are explored in this proposal, which are hardware algorithms for mapping and P&R in fine grain devices, and binary translation coupled with reconfiguration for coarse grain devices. As the hardware itself is responsible for its adaptation to the new scenario, this opens up several application possibilities besides optimum execution times or energy efficiency. We will show two case studies that explore the initial ideas of this work, and discuss the problems that lie ahead of this adaptive computing path. One case study is a JIT modulo scheduling algorithm for inner loop acceleration. The second case is a runt-ime FPGA placement and routing. 


Ricardo dos Santos Ferreira is an Associate professor in the Department of Informatics DPI, Unversidade Federal de Vicosa, Brazil. During 2012/2013, he was in a sabbatical  at TU-Delft.  He received a PhD in Electrical and Computer Engineering  from the Universite catholique de Louvain in 1999. His research interests include: Run-time Reconfigurable Computing and Embedded Systems, FPGA and GPU for HPC, Placement  and Routing, Technology Mapping, Power Estimation, Bioinformatics, and Binary Decision Diagrams. 


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