Towards Shared-Memory Reconfigurable Computing in Server Systems

Speaker

H. Peter Hofstee from IBM Austin Research Laboratory -- 16-11-2012

Abstract

In this talk we describe some recent prototype systems that combine conventional Power processors with reconfigurable acceleration (FPGAs). The goal of this work is to create systems that allow us to accelerate "single thread" computations and also to improve efficiency for throughput computing. Ultimately, the goal of this work is to enable an infrastructure in which the reconfigurable logic is as easy to program and to use as conventional processors. We discuss an organization that maintains architectural integrity and lay out some of the challenges, most specifically to the runtimes of such processors. We also discuss the role of some recent efforts, such as OpenCL for FPGAs and LiMe in the context of this broader objective.

Bio

H. Peter Hofstee currently works at the IBM Austin Research Laboratory on workload-optimized and hybrid systems. Peter has degrees in theoretical physics (MS, Rijks Universiteit Groningen, Netherlands) and computer science (PhD, California Inst. of Technology). At IBM Peter has worked on microprocessors, including the first CMOS processor to demonstrate GHz operation (1997), and he was the chief architect of the synergistic processor elements in the Cell Broadband Engine, known from its use in the Sony Playstation 3 and the Roadrunner supercomputer that first broke the 1 Petaflop Linpack benchmark. His interests include VLSI, multicore and heterogeneous microprocessor architecture, security, system design and programming. Peter has over 100 patents issued or pending.

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